A novel high-speed and highly reliable sense-amplifier-based flip-flop with transition completion detection (SAFF-TCD) is proposed for low supply voltage (VDD) operation. The SAFF-TCD adopts the internally generated detection signal to indicate the completion of sense-amplifier stage transition. The detection signal gates the pull-down path of the sense-amplifier stage and the slave latch, thus overcoming the operational yield degradation, current contention, and glitches of previous SAFFs. The operational yield, speed, hold time, energy consumption, and area of the proposed and previous FFs are quantitatively compared for a wide range of VDD with 22-nm FinFET technology. It is shown that the minimum VDD of the SAFF-TCD is 573 mV lower than that of previous SAFFs, which means the SAFF-TCD can operate even when VDD is in the near-threshold or subthreshold region. At 0.3-0.4 V, the SAFF-TCD operates twice as fast as the master-slave-based FF (MSFF) with a practical hold time. Even with these benefits, the energy consumption overhead is limited to less than 20% compared with that of MSFF, and the area is similar to that of previous SAFFs.
|Number of pages||12|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|Publication status||Published - 2018 Apr|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering