TY - JOUR
T1 - Sensing margin enhancement technique utilizing boosted reference voltage for low-voltage and high-density dram
AU - Kim, Suk Min
AU - Song, Byungkyu
AU - Jung, Seong Ook
N1 - Publisher Copyright:
© 1993-2012 IEEE.
Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2019/10
Y1 - 2019/10
N2 - In the case of dynamic random access memory (DRAM) using a voltage latched sense amplifier, various offset voltage cancellation techniques have been studied to secure the sensing margin. However, as coupling noise and process variations increase with technology scaling, it is impossible to obtain a sufficient sensing margin only by using an offset voltage cancellation technique. In addition, offset voltage cancellation techniques have several problems, such as area overhead and sensing speed slowdown at a low supply voltage. In this paper, we propose a sense amplifier that maximizes the sensing margin by boosting the reference bitline voltage during the charge sharing operation and adopting the offset voltage cancellation technique. The sensing voltage difference of the proposed sense amplifier increases by 50% or more than that of the conventional offset cancellation (OC) sense amplifier at the low supply voltage of 0.9 V, which can improve not only the sensing speed by 2 ns but also the sensing yield by 11.8%. In addition, the proposed sense amplifier achieves a stable sensing yield with a larger cell array height and thus can compensate the area overhead of 44% caused by the OC technique by decreasing the overall cell array height.
AB - In the case of dynamic random access memory (DRAM) using a voltage latched sense amplifier, various offset voltage cancellation techniques have been studied to secure the sensing margin. However, as coupling noise and process variations increase with technology scaling, it is impossible to obtain a sufficient sensing margin only by using an offset voltage cancellation technique. In addition, offset voltage cancellation techniques have several problems, such as area overhead and sensing speed slowdown at a low supply voltage. In this paper, we propose a sense amplifier that maximizes the sensing margin by boosting the reference bitline voltage during the charge sharing operation and adopting the offset voltage cancellation technique. The sensing voltage difference of the proposed sense amplifier increases by 50% or more than that of the conventional offset cancellation (OC) sense amplifier at the low supply voltage of 0.9 V, which can improve not only the sensing speed by 2 ns but also the sensing yield by 11.8%. In addition, the proposed sense amplifier achieves a stable sensing yield with a larger cell array height and thus can compensate the area overhead of 44% caused by the OC technique by decreasing the overall cell array height.
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U2 - 10.1109/TVLSI.2019.2920630
DO - 10.1109/TVLSI.2019.2920630
M3 - Article
AN - SCOPUS:85077717330
VL - 27
SP - 2413
EP - 2422
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 10
M1 - 8744261
ER -