Sensing voltage compensation circuit for low-power dram bit-line sense amplifier

Suk Min Kim, Tae Woo Oh, Seong Ook Jung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

As the DRAM process technology scales down, the offset voltage caused by the VTH mismatch between the Latch Transistors of Bit-Line Sense Amplifier (BLSA) tends to increase further. This offset voltage eventually leads to a data read failure by reducing the sensing voltage. To solve this problem, various types of offset cancellation BLSA have been studied. In addition to the offset voltage, the sensing noise between adjacent bit lines is another major cause of reduced sensing voltage. The solution to this problem is also necessary as the minimum feature size of the DRAM cell decreases. In this paper, we propose a Sensing Voltage Compensation (SVC) circuit for DRAM BLSA that can solve both problems simultaneously.

Original languageEnglish
Title of host publicationInternational Conference on Electronics, Information and Communication, ICEIC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-4
Number of pages4
ISBN (Electronic)9781538647547
DOIs
Publication statusPublished - 2018 Apr 2
Event17th International Conference on Electronics, Information and Communication, ICEIC 2018 - Honolulu, United States
Duration: 2018 Jan 242018 Jan 27

Publication series

NameInternational Conference on Electronics, Information and Communication, ICEIC 2018
Volume2018-January

Other

Other17th International Conference on Electronics, Information and Communication, ICEIC 2018
CountryUnited States
CityHonolulu
Period18/1/2418/1/27

All Science Journal Classification (ASJC) codes

  • Information Systems
  • Computer Networks and Communications
  • Computer Science Applications
  • Signal Processing
  • Electrical and Electronic Engineering

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