Microarchitecture is difficult to be evaluated on the silicon level, due to the time and cost. Accordingly, most researches rely on cycle-accurate simulators to evaluate the performance. At the time of development, the cycle-accurate simulator must have been validated. However, off-the-shelf processors have been continuously improved, since the cycle-accurate simulator was developed. Thus, the improved features should be implemented into the simulator for accurate performance evaluation. In order to explore the accuracy of the cycle-accurate simulator, we modified the cycle-accurate model (Sim-Outorder) of Simplescalar suite to adopt off-the-shelf processor (ARM1136) features. The difference between the IPC (instruction per cycle) of the modified model (Sim-ARM1136) and the IPC of the original model (Sim-Outorder) is 19%, on average. Furthermore, it is difficult to find a relation between the simulation results from Sim-ARM1136 and those from Sim-Outorder, which might mislead to different conclusions.
|Number of pages||8|
|Journal||Microprocessors and Microsystems|
|Publication status||Published - 2006 May 5|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Computer Networks and Communications
- Artificial Intelligence