Abstract
Most of the available path-delay fault simulators for scan environments rely on the use of augmented scan flip-flops and exclusively consider circuits composed of only discrete gates This paper describes an efficient path-delay fault simulator which operates in standard scan environments The new simulator based on a parallel pattern fault simulation algorithm can handle the switching devices by using new logic values To achieve high-speed performance, two different sets of logic values are used for the element evaluation according to the device level The results show the efficiency of the simulator.
| Original language | English |
|---|---|
| Pages (from-to) | 236-242 |
| Number of pages | 7 |
| Journal | IEE Proceedings: Circuits, Devices and Systems |
| Volume | 144 |
| Issue number | 4 |
| DOIs | |
| Publication status | Published - 1997 Jan 1 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
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Simulator for path-delay faults on mixed-level circuits. / Yim, Y. T.; Kang, Y. S.; Kang, Sungho.
In: IEE Proceedings: Circuits, Devices and Systems, Vol. 144, No. 4, 01.01.1997, p. 236-242.Research output: Contribution to journal › Article
TY - JOUR
T1 - Simulator for path-delay faults on mixed-level circuits
AU - Yim, Y. T.
AU - Kang, Y. S.
AU - Kang, Sungho
PY - 1997/1/1
Y1 - 1997/1/1
N2 - Most of the available path-delay fault simulators for scan environments rely on the use of augmented scan flip-flops and exclusively consider circuits composed of only discrete gates This paper describes an efficient path-delay fault simulator which operates in standard scan environments The new simulator based on a parallel pattern fault simulation algorithm can handle the switching devices by using new logic values To achieve high-speed performance, two different sets of logic values are used for the element evaluation according to the device level The results show the efficiency of the simulator.
AB - Most of the available path-delay fault simulators for scan environments rely on the use of augmented scan flip-flops and exclusively consider circuits composed of only discrete gates This paper describes an efficient path-delay fault simulator which operates in standard scan environments The new simulator based on a parallel pattern fault simulation algorithm can handle the switching devices by using new logic values To achieve high-speed performance, two different sets of logic values are used for the element evaluation according to the device level The results show the efficiency of the simulator.
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UR - http://www.scopus.com/inward/citedby.url?scp=0031209567&partnerID=8YFLogxK
U2 - 10.1049/ip-cds:19971287
DO - 10.1049/ip-cds:19971287
M3 - Article
AN - SCOPUS:0031209567
VL - 144
SP - 236
EP - 242
JO - IET Circuits, Devices and Systems
JF - IET Circuits, Devices and Systems
SN - 1751-858X
IS - 4
ER -