This paper proposes a microarchitectural mechanism to minimize the latency of thread migration for a tightly-coupled heterogeneous core, which has two execution backends (e.g., in-order and out-of-order execution pipelines). The proposed mechanism examines the dependencies between all in-flight instructions that reside in one of the backend pipelines, and allows both pipelines to simultaneously perform the instruction execution. At the microarchitectural level, instruction dispatching and instruction execution are seamlessly performed across thread migration, and therefore, this simultaneous backend execution can accelerate the program execution, which cannot be achieved with an existing migration mechanism. Accelerating thread migration will increase the overall performance with low power overhead, providing high energy efficiency. As compared to a baseline heterogeneous core with an existing migration mechanism, the simultaneous backend execution reduces 8.2 percent of the total execution cycle and consumes 2.9 percent lower total energy on average across SPEC CPU2006 benchmarks, which results in an improved energy efficiency of 10.9 percent in terms of the energy-delay product.
All Science Journal Classification (ASJC) codes
- Theoretical Computer Science
- Hardware and Architecture
- Computational Theory and Mathematics