Single chip array processor for high performance design error simulation

Sungho Kang, Stephen A. Szygenda

Research output: Contribution to journalConference article

Abstract

This paper describes a single chip massively parallel special array processor which can be used as a new high performance accelerator for design error simulation. The new accelerator adopts simple logic element and communication interface with minimum transistors. Using this, high speed simulation can be performed.

Original languageEnglish
Pages (from-to)338-341
Number of pages4
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
Publication statusPublished - 1995 Dec 1

Fingerprint

Parallel processing systems
Particle accelerators
Transistors
Communication

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

@article{41e665eae7da4728b8bb453b228fe555,
title = "Single chip array processor for high performance design error simulation",
abstract = "This paper describes a single chip massively parallel special array processor which can be used as a new high performance accelerator for design error simulation. The new accelerator adopts simple logic element and communication interface with minimum transistors. Using this, high speed simulation can be performed.",
author = "Sungho Kang and Szygenda, {Stephen A.}",
year = "1995",
month = "12",
day = "1",
language = "English",
pages = "338--341",
journal = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",
issn = "1063-0988",

}

Single chip array processor for high performance design error simulation. / Kang, Sungho; Szygenda, Stephen A.

In: Proceedings of the Annual IEEE International ASIC Conference and Exhibit, 01.12.1995, p. 338-341.

Research output: Contribution to journalConference article

TY - JOUR

T1 - Single chip array processor for high performance design error simulation

AU - Kang, Sungho

AU - Szygenda, Stephen A.

PY - 1995/12/1

Y1 - 1995/12/1

N2 - This paper describes a single chip massively parallel special array processor which can be used as a new high performance accelerator for design error simulation. The new accelerator adopts simple logic element and communication interface with minimum transistors. Using this, high speed simulation can be performed.

AB - This paper describes a single chip massively parallel special array processor which can be used as a new high performance accelerator for design error simulation. The new accelerator adopts simple logic element and communication interface with minimum transistors. Using this, high speed simulation can be performed.

UR - http://www.scopus.com/inward/record.url?scp=0029504462&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029504462&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0029504462

SP - 338

EP - 341

JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

SN - 1063-0988

ER -