Single chip array processor for high performance design error simulation

Sungho Kang, Stephen A. Szygenda

Research output: Contribution to journalConference article

Abstract

This paper describes a single chip massively parallel special array processor which can be used as a new high performance accelerator for design error simulation. The new accelerator adopts simple logic element and communication interface with minimum transistors. Using this, high speed simulation can be performed.

Original languageEnglish
Pages (from-to)338-341
Number of pages4
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
Publication statusPublished - 1995
EventProceedings of the 8th Annual IEEE International ASIC Conference and Exhibit - Austin, TX, USA
Duration: 1995 Sep 181995 Sep 22

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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