Single-ended and differential phased array front-ends are developed for Ka-band applications using a 0.12 μm SiGe BiCMOS process. The phase shifters are based on CMOS switched delay networks and have 22.5° phase resolution and <4° rms phase error at 35 GHz, and can handle +10 dBm of RF power (P1dB) with a 3rd order intermodulation intercept point (IIP3) of +21 dBm. For the single-ended design, a SiGe low noise amplifier is placed before the CMOS phase shifter, and the LNA/phase shifter results in 11 ± 1.5 dB gain and < 3.4 dB of noise figure (NF), for a total power consumption of only 11 mW. For the differential front-end, a variable gain LNA is also developed and shows 9-20 dB gain and < 1° rms phase imbalance between the eight different gain states. The differential variable gain LNA/phase shifter consumes 33 mW, and results in 10 ± 1.3 dB gain and 3.8 dB of NF. The gain variation is reduced to 9.1 ± 0.45 dB with the variable gain function applied. The single-ended and differential front-ends occupy a small chip area, with a size of 350 × 800 μm2 and 350 × 950 μm 3, respectively, excluding pads. These chips are competitive with GaAs and InP designs, and are building blocks for low-cost millimeter-wave phased array front-ends based on silicon technology.
Bibliographical noteFunding Information:
Manuscript received August 24, 2007; revised June 19, 2008. Current version published October 8, 2008. This work was supported by the U.S. Army Research Laboratories under Collaborative Technology Agreement (CTA).
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering