Single-error-correction and double-adjacent-error-correction code for simultaneous testing of data bit and check bit arrays in memories

Sanguhn Cha, Hongil Yoon

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

In this paper, a new single-error-correction and double-adjacent-error- correction (SEC-DAEC) code is proposed for simultaneous testing of the most general memory fault models in both data bit and check bit arrays of memories. Simultaneous testing of data bit and check bit arrays eliminates the test time and hardware overheads required for separate check bit array tests. In order to test data bit and check bit arrays simultaneously, the proposed SEC-DAEC code generates the identical data background patterns for data bit and check bit arrays. The testable faults using the proposed SEC-DAEC code are the most general memory fault models such as single-cell faults and interword and intraword coupling faults. Simultaneous testing of data bit and check bit arrays using the proposed SEC-DAEC codes brings significant decreases of about 27.3%, 17.9%, and 11.1% in the time required for memory array tests for 16, 32, and 64 data bits per word, respectively. In addition, the number of ones in the H-matrix of the proposed SEC-DAEC code is brought close to the theoretical minimum number, thereby reducing the complexity of the check bit generator.

Original languageEnglish
Article number6709746
Pages (from-to)529-535
Number of pages7
JournalIEEE Transactions on Device and Materials Reliability
Volume14
Issue number1
DOIs
Publication statusPublished - 2014 Mar

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Error correction
Data storage equipment
Testing

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Safety, Risk, Reliability and Quality
  • Electrical and Electronic Engineering

Cite this

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title = "Single-error-correction and double-adjacent-error-correction code for simultaneous testing of data bit and check bit arrays in memories",
abstract = "In this paper, a new single-error-correction and double-adjacent-error- correction (SEC-DAEC) code is proposed for simultaneous testing of the most general memory fault models in both data bit and check bit arrays of memories. Simultaneous testing of data bit and check bit arrays eliminates the test time and hardware overheads required for separate check bit array tests. In order to test data bit and check bit arrays simultaneously, the proposed SEC-DAEC code generates the identical data background patterns for data bit and check bit arrays. The testable faults using the proposed SEC-DAEC code are the most general memory fault models such as single-cell faults and interword and intraword coupling faults. Simultaneous testing of data bit and check bit arrays using the proposed SEC-DAEC codes brings significant decreases of about 27.3{\%}, 17.9{\%}, and 11.1{\%} in the time required for memory array tests for 16, 32, and 64 data bits per word, respectively. In addition, the number of ones in the H-matrix of the proposed SEC-DAEC code is brought close to the theoretical minimum number, thereby reducing the complexity of the check bit generator.",
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N2 - In this paper, a new single-error-correction and double-adjacent-error- correction (SEC-DAEC) code is proposed for simultaneous testing of the most general memory fault models in both data bit and check bit arrays of memories. Simultaneous testing of data bit and check bit arrays eliminates the test time and hardware overheads required for separate check bit array tests. In order to test data bit and check bit arrays simultaneously, the proposed SEC-DAEC code generates the identical data background patterns for data bit and check bit arrays. The testable faults using the proposed SEC-DAEC code are the most general memory fault models such as single-cell faults and interword and intraword coupling faults. Simultaneous testing of data bit and check bit arrays using the proposed SEC-DAEC codes brings significant decreases of about 27.3%, 17.9%, and 11.1% in the time required for memory array tests for 16, 32, and 64 data bits per word, respectively. In addition, the number of ones in the H-matrix of the proposed SEC-DAEC code is brought close to the theoretical minimum number, thereby reducing the complexity of the check bit generator.

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