Single-error-correction code for simultaneous testing of data bit and check bit arrays for word-oriented memories

Sanguhn Cha, Hong Il Yoon

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

A novel single-error-correction (SEC) code is proposed in order to test various fault models simultaneously in both data bit and check bit arrays for word-oriented memories (WOMs). Simultaneous testing of data bit and check bit arrays eliminates the test time and hardware overheads required for separate check bit array tests. The testable faults using the proposed SEC code are the most well-known memory fault models such as single-cell faults and interword and intraword coupling faults. The regularity in data backgrounds (DBs) corresponding to these fault models for WOM tests is investigated. Henceforth, the proposed SEC code is constructed to generate the identical DB patterns for data bit and check bit arrays. Simultaneous testing of data bit and check bit arrays using the proposed SEC codes brings a significant decrease of about 9.9%-33.3% in the time required for memory array tests for 8, 16, 32, and 64 data bits per word. In addition, the number of ones in the H -matrix of the proposed SEC code is brought close to the theoretical minimum number, thereby reducing the complexity of the check bit generator. For various applications, the proposed SEC code can be represented by many forms of H-matrices.

Original languageEnglish
Article number6401179
Pages (from-to)266-271
Number of pages6
JournalIEEE Transactions on Device and Materials Reliability
Volume13
Issue number1
DOIs
Publication statusPublished - 2013 Mar 19

Fingerprint

Error correction
Data storage equipment
Testing
Hardware

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Safety, Risk, Reliability and Quality
  • Electrical and Electronic Engineering

Cite this

@article{2475f3ce4ed541c088b829ee58ed6279,
title = "Single-error-correction code for simultaneous testing of data bit and check bit arrays for word-oriented memories",
abstract = "A novel single-error-correction (SEC) code is proposed in order to test various fault models simultaneously in both data bit and check bit arrays for word-oriented memories (WOMs). Simultaneous testing of data bit and check bit arrays eliminates the test time and hardware overheads required for separate check bit array tests. The testable faults using the proposed SEC code are the most well-known memory fault models such as single-cell faults and interword and intraword coupling faults. The regularity in data backgrounds (DBs) corresponding to these fault models for WOM tests is investigated. Henceforth, the proposed SEC code is constructed to generate the identical DB patterns for data bit and check bit arrays. Simultaneous testing of data bit and check bit arrays using the proposed SEC codes brings a significant decrease of about 9.9{\%}-33.3{\%} in the time required for memory array tests for 8, 16, 32, and 64 data bits per word. In addition, the number of ones in the H -matrix of the proposed SEC code is brought close to the theoretical minimum number, thereby reducing the complexity of the check bit generator. For various applications, the proposed SEC code can be represented by many forms of H-matrices.",
author = "Sanguhn Cha and Yoon, {Hong Il}",
year = "2013",
month = "3",
day = "19",
doi = "10.1109/TDMR.2013.2237774",
language = "English",
volume = "13",
pages = "266--271",
journal = "IEEE Transactions on Device and Materials Reliability",
issn = "1530-4388",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "1",

}

Single-error-correction code for simultaneous testing of data bit and check bit arrays for word-oriented memories. / Cha, Sanguhn; Yoon, Hong Il.

In: IEEE Transactions on Device and Materials Reliability, Vol. 13, No. 1, 6401179, 19.03.2013, p. 266-271.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Single-error-correction code for simultaneous testing of data bit and check bit arrays for word-oriented memories

AU - Cha, Sanguhn

AU - Yoon, Hong Il

PY - 2013/3/19

Y1 - 2013/3/19

N2 - A novel single-error-correction (SEC) code is proposed in order to test various fault models simultaneously in both data bit and check bit arrays for word-oriented memories (WOMs). Simultaneous testing of data bit and check bit arrays eliminates the test time and hardware overheads required for separate check bit array tests. The testable faults using the proposed SEC code are the most well-known memory fault models such as single-cell faults and interword and intraword coupling faults. The regularity in data backgrounds (DBs) corresponding to these fault models for WOM tests is investigated. Henceforth, the proposed SEC code is constructed to generate the identical DB patterns for data bit and check bit arrays. Simultaneous testing of data bit and check bit arrays using the proposed SEC codes brings a significant decrease of about 9.9%-33.3% in the time required for memory array tests for 8, 16, 32, and 64 data bits per word. In addition, the number of ones in the H -matrix of the proposed SEC code is brought close to the theoretical minimum number, thereby reducing the complexity of the check bit generator. For various applications, the proposed SEC code can be represented by many forms of H-matrices.

AB - A novel single-error-correction (SEC) code is proposed in order to test various fault models simultaneously in both data bit and check bit arrays for word-oriented memories (WOMs). Simultaneous testing of data bit and check bit arrays eliminates the test time and hardware overheads required for separate check bit array tests. The testable faults using the proposed SEC code are the most well-known memory fault models such as single-cell faults and interword and intraword coupling faults. The regularity in data backgrounds (DBs) corresponding to these fault models for WOM tests is investigated. Henceforth, the proposed SEC code is constructed to generate the identical DB patterns for data bit and check bit arrays. Simultaneous testing of data bit and check bit arrays using the proposed SEC codes brings a significant decrease of about 9.9%-33.3% in the time required for memory array tests for 8, 16, 32, and 64 data bits per word. In addition, the number of ones in the H -matrix of the proposed SEC code is brought close to the theoretical minimum number, thereby reducing the complexity of the check bit generator. For various applications, the proposed SEC code can be represented by many forms of H-matrices.

UR - http://www.scopus.com/inward/record.url?scp=84874966074&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84874966074&partnerID=8YFLogxK

U2 - 10.1109/TDMR.2013.2237774

DO - 10.1109/TDMR.2013.2237774

M3 - Article

AN - SCOPUS:84874966074

VL - 13

SP - 266

EP - 271

JO - IEEE Transactions on Device and Materials Reliability

JF - IEEE Transactions on Device and Materials Reliability

SN - 1530-4388

IS - 1

M1 - 6401179

ER -