A novel single-error-correction (SEC) code is proposed in order to test various fault models simultaneously in both data bit and check bit arrays for word-oriented memories (WOMs). Simultaneous testing of data bit and check bit arrays eliminates the test time and hardware overheads required for separate check bit array tests. The testable faults using the proposed SEC code are the most well-known memory fault models such as single-cell faults and interword and intraword coupling faults. The regularity in data backgrounds (DBs) corresponding to these fault models for WOM tests is investigated. Henceforth, the proposed SEC code is constructed to generate the identical DB patterns for data bit and check bit arrays. Simultaneous testing of data bit and check bit arrays using the proposed SEC codes brings a significant decrease of about 9.9%-33.3% in the time required for memory array tests for 8, 16, 32, and 64 data bits per word. In addition, the number of ones in the H -matrix of the proposed SEC code is brought close to the theoretical minimum number, thereby reducing the complexity of the check bit generator. For various applications, the proposed SEC code can be represented by many forms of H-matrices.
|Number of pages||6|
|Journal||IEEE Transactions on Device and Materials Reliability|
|Publication status||Published - 2013 Mar 19|
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Safety, Risk, Reliability and Quality
- Electrical and Electronic Engineering