Slope interconnect effort: Gate-interconnect interdependent delay modeling for early CMOS circuit simulation

Myeong Eun Hwang; Seong Ook Jung; Kaushik Roy

doi:10.1109/TCSI.2008.2006217

Slope interconnect effort: Gate-interconnect interdependent delay modeling for early CMOS circuit simulation

Myeong Eun Hwang, Seong Ook Jung, Kaushik Roy

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

33 Citations (Scopus)

Abstract

We propose an analytical closed-form gate-interconnect interdependent delay model that accounts for the dynamic behavior of signal slope across different regions of operation. In the presence of interconnects, the gate driver influences the input slope of the driven wire affecting the interconnect delay, and the driven wire acts as a parasitic load to the driver affecting the gate delay. Hence, it is essential to consider their interdependence for an accurate estimation of the circuit delay. The proposed model converts a signal slope into its effective fan-out for a simple yet accurate delay estimation. Simulations show that, for ISCAS benchmark circuits, our framework exhibits an error of < 5.3% at each stage and < 4.3% for the path delay with a speedup of three orders of magnitude over HSPICE at the 130-nm technology node. Two test chips have been fabricated in 90- and 65-nm CMOS technologies to verify the effectiveness of the proposed model. Measured results show that, for a wide range of interconnect lengths (2000 and 1400 μm) and geometries, the proposed model predicts the circuit delay with an error of 5.7% at a supply voltage of V_dd = 1.2 V and 4.8% at V_dd = 0.3 V.

Original language	English
Pages (from-to)	1427-1440
Number of pages	14
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	56
Issue number	7
DOIs	https://doi.org/10.1109/TCSI.2008.2006217
Publication status	Published - 2009

Bibliographical note

Funding Information:
Manuscript received October 06, 2007; revised June 19, 2008. First published November 11, 2008; current version published July 06, 2009. This work was supported in part by the Defense Advanced Research Projects Agency, by the Semiconductor Research Corporation, and by Qualcomm, Inc. This paper was recommended by Associate Editor V. De. M.-E. Hwang is with Intel Corporation, Hillsboro, OR 97124 USA (e-mail: hwangm@ecn.purdue.edu). S.-O. Jung is with the Department of Electrical and Computer Engineering, Yonsei University, Seoul 120-749, Korea (e-mail: sjung@yonsei.ac.kr). K. Roy is with the Department Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907 USA (e-mail: kaushik@ece.purdue.edu). Digital Object Identifier 10.1109/TCSI.2008.2006217

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/TCSI.2008.2006217

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title = "Slope interconnect effort: Gate-interconnect interdependent delay modeling for early CMOS circuit simulation",

abstract = "We propose an analytical closed-form gate-interconnect interdependent delay model that accounts for the dynamic behavior of signal slope across different regions of operation. In the presence of interconnects, the gate driver influences the input slope of the driven wire affecting the interconnect delay, and the driven wire acts as a parasitic load to the driver affecting the gate delay. Hence, it is essential to consider their interdependence for an accurate estimation of the circuit delay. The proposed model converts a signal slope into its effective fan-out for a simple yet accurate delay estimation. Simulations show that, for ISCAS benchmark circuits, our framework exhibits an error of < 5.3% at each stage and < 4.3% for the path delay with a speedup of three orders of magnitude over HSPICE at the 130-nm technology node. Two test chips have been fabricated in 90- and 65-nm CMOS technologies to verify the effectiveness of the proposed model. Measured results show that, for a wide range of interconnect lengths (2000 and 1400 μm) and geometries, the proposed model predicts the circuit delay with an error of 5.7% at a supply voltage of Vdd = 1.2 V and 4.8% at Vdd = 0.3 V.",

author = "Hwang, {Myeong Eun} and Jung, {Seong Ook} and Kaushik Roy",

note = "Funding Information: Manuscript received October 06, 2007; revised June 19, 2008. First published November 11, 2008; current version published July 06, 2009. This work was supported in part by the Defense Advanced Research Projects Agency, by the Semiconductor Research Corporation, and by Qualcomm, Inc. This paper was recommended by Associate Editor V. De. M.-E. Hwang is with Intel Corporation, Hillsboro, OR 97124 USA (e-mail: hwangm@ecn.purdue.edu). S.-O. Jung is with the Department of Electrical and Computer Engineering, Yonsei University, Seoul 120-749, Korea (e-mail: sjung@yonsei.ac.kr). K. Roy is with the Department Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907 USA (e-mail: kaushik@ece.purdue.edu). Digital Object Identifier 10.1109/TCSI.2008.2006217",

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N1 - Funding Information: Manuscript received October 06, 2007; revised June 19, 2008. First published November 11, 2008; current version published July 06, 2009. This work was supported in part by the Defense Advanced Research Projects Agency, by the Semiconductor Research Corporation, and by Qualcomm, Inc. This paper was recommended by Associate Editor V. De. M.-E. Hwang is with Intel Corporation, Hillsboro, OR 97124 USA (e-mail: hwangm@ecn.purdue.edu). S.-O. Jung is with the Department of Electrical and Computer Engineering, Yonsei University, Seoul 120-749, Korea (e-mail: sjung@yonsei.ac.kr). K. Roy is with the Department Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907 USA (e-mail: kaushik@ece.purdue.edu). Digital Object Identifier 10.1109/TCSI.2008.2006217

PY - 2009

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N2 - We propose an analytical closed-form gate-interconnect interdependent delay model that accounts for the dynamic behavior of signal slope across different regions of operation. In the presence of interconnects, the gate driver influences the input slope of the driven wire affecting the interconnect delay, and the driven wire acts as a parasitic load to the driver affecting the gate delay. Hence, it is essential to consider their interdependence for an accurate estimation of the circuit delay. The proposed model converts a signal slope into its effective fan-out for a simple yet accurate delay estimation. Simulations show that, for ISCAS benchmark circuits, our framework exhibits an error of < 5.3% at each stage and < 4.3% for the path delay with a speedup of three orders of magnitude over HSPICE at the 130-nm technology node. Two test chips have been fabricated in 90- and 65-nm CMOS technologies to verify the effectiveness of the proposed model. Measured results show that, for a wide range of interconnect lengths (2000 and 1400 μm) and geometries, the proposed model predicts the circuit delay with an error of 5.7% at a supply voltage of Vdd = 1.2 V and 4.8% at Vdd = 0.3 V.

AB - We propose an analytical closed-form gate-interconnect interdependent delay model that accounts for the dynamic behavior of signal slope across different regions of operation. In the presence of interconnects, the gate driver influences the input slope of the driven wire affecting the interconnect delay, and the driven wire acts as a parasitic load to the driver affecting the gate delay. Hence, it is essential to consider their interdependence for an accurate estimation of the circuit delay. The proposed model converts a signal slope into its effective fan-out for a simple yet accurate delay estimation. Simulations show that, for ISCAS benchmark circuits, our framework exhibits an error of < 5.3% at each stage and < 4.3% for the path delay with a speedup of three orders of magnitude over HSPICE at the 130-nm technology node. Two test chips have been fabricated in 90- and 65-nm CMOS technologies to verify the effectiveness of the proposed model. Measured results show that, for a wide range of interconnect lengths (2000 and 1400 μm) and geometries, the proposed model predicts the circuit delay with an error of 5.7% at a supply voltage of Vdd = 1.2 V and 4.8% at Vdd = 0.3 V.

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ER -

Slope interconnect effort: Gate-interconnect interdependent delay modeling for early CMOS circuit simulation

Abstract

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