Slope interconnect effort: Gate-interconnect interdependentdelay model for CMOS logic gates

Myeong Eun Hwang, Seong Ook Jung, Kaushik Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

We present a circuit delay framework in a closed form that accounts for the dynamic behavior of signal slope in subthreshold (VDD VT) as well as superthreshold (VDD > VT) regions. The proposed model converts a signal slope into its effective fanout for delay estimation. Simulations show that for ISCAS benchmark circuits, our framework exhibits a speedup of three orders of magnitude over HSPICE with 5% error. Measured results in 65nm show that for a wide range of interconnect lengths and geometries, the proposed model predicts the circuit delay with 5.7% error at the supply voltage of VDD = 1.2V , and with 4.5% error at VDD = 0.4V .

Original languageEnglish
Title of host publicationISLPED'07
Subtitle of host publicationProceedings of the 2007 International Symposium on Low Power Electronics and Design
Pages387-390
Number of pages4
DOIs
Publication statusPublished - 2007 Dec 17
EventISLPED'07: 2007 International Symposium on Low Power Electronics and Design - Portland, OR, United States
Duration: 2007 Aug 272007 Aug 29

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

OtherISLPED'07: 2007 International Symposium on Low Power Electronics and Design
CountryUnited States
CityPortland, OR
Period07/8/2707/8/29

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All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Hwang, M. E., Jung, S. O., & Roy, K. (2007). Slope interconnect effort: Gate-interconnect interdependentdelay model for CMOS logic gates. In ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design (pp. 387-390). (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1145/1283780.1283865