Slope interconnect effort: Gate-interconnect interdependentdelay model for CMOS logic gates

Myeong Eun Hwang; Seong Ook Jung; Kaushik Roy

doi:10.1145/1283780.1283865

Slope interconnect effort: Gate-interconnect interdependentdelay model for CMOS logic gates

Myeong Eun Hwang, Seong Ook Jung, Kaushik Roy

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

We present a circuit delay framework in a closed form that accounts for the dynamic behavior of signal slope in subthreshold (V_DD V_T) as well as superthreshold (V_DD > V_T) regions. The proposed model converts a signal slope into its effective fanout for delay estimation. Simulations show that for ISCAS benchmark circuits, our framework exhibits a speedup of three orders of magnitude over HSPICE with 5% error. Measured results in 65nm show that for a wide range of interconnect lengths and geometries, the proposed model predicts the circuit delay with 5.7% error at the supply voltage of V_DD = 1.2V , and with 4.5% error at V_DD = 0.4V .

Original language	English
Title of host publication	ISLPED'07
Subtitle of host publication	Proceedings of the 2007 International Symposium on Low Power Electronics and Design
Pages	387-390
Number of pages	4
DOIs	https://doi.org/10.1145/1283780.1283865
Publication status	Published - 2007
Event	ISLPED'07: 2007 International Symposium on Low Power Electronics and Design - Portland, OR, United States Duration: 2007 Aug 27 → 2007 Aug 29

Publication series

Name	Proceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)	1533-4678

Other

Other	ISLPED'07: 2007 International Symposium on Low Power Electronics and Design
Country/Territory	United States
City	Portland, OR
Period	07/8/27 → 07/8/29

All Science Journal Classification (ASJC) codes

Engineering(all)

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10.1145/1283780.1283865

Cite this

Hwang, M. E., Jung, S. O., & Roy, K. (2007). Slope interconnect effort: Gate-interconnect interdependentdelay model for CMOS logic gates. In ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design (pp. 387-390). (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1145/1283780.1283865

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title = "Slope interconnect effort: Gate-interconnect interdependentdelay model for CMOS logic gates",

abstract = "We present a circuit delay framework in a closed form that accounts for the dynamic behavior of signal slope in subthreshold (VDD VT) as well as superthreshold (VDD > VT) regions. The proposed model converts a signal slope into its effective fanout for delay estimation. Simulations show that for ISCAS benchmark circuits, our framework exhibits a speedup of three orders of magnitude over HSPICE with 5% error. Measured results in 65nm show that for a wide range of interconnect lengths and geometries, the proposed model predicts the circuit delay with 5.7% error at the supply voltage of VDD = 1.2V , and with 4.5% error at VDD = 0.4V .",

author = "Hwang, {Myeong Eun} and Jung, {Seong Ook} and Kaushik Roy",

year = "2007",

doi = "10.1145/1283780.1283865",

language = "English",

isbn = "1595937099",

series = "Proceedings of the International Symposium on Low Power Electronics and Design",

pages = "387--390",

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note = "ISLPED'07: 2007 International Symposium on Low Power Electronics and Design ; Conference date: 27-08-2007 Through 29-08-2007",

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Hwang, ME, Jung, SO & Roy, K 2007, Slope interconnect effort: Gate-interconnect interdependentdelay model for CMOS logic gates. in ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design. Proceedings of the International Symposium on Low Power Electronics and Design, pp. 387-390, ISLPED'07: 2007 International Symposium on Low Power Electronics and Design, Portland, OR, United States, 07/8/27. https://doi.org/10.1145/1283780.1283865

Slope interconnect effort : Gate-interconnect interdependentdelay model for CMOS logic gates. / Hwang, Myeong Eun; Jung, Seong Ook; Roy, Kaushik.

ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design. 2007. p. 387-390 (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - We present a circuit delay framework in a closed form that accounts for the dynamic behavior of signal slope in subthreshold (VDD VT) as well as superthreshold (VDD > VT) regions. The proposed model converts a signal slope into its effective fanout for delay estimation. Simulations show that for ISCAS benchmark circuits, our framework exhibits a speedup of three orders of magnitude over HSPICE with 5% error. Measured results in 65nm show that for a wide range of interconnect lengths and geometries, the proposed model predicts the circuit delay with 5.7% error at the supply voltage of VDD = 1.2V , and with 4.5% error at VDD = 0.4V .

AB - We present a circuit delay framework in a closed form that accounts for the dynamic behavior of signal slope in subthreshold (VDD VT) as well as superthreshold (VDD > VT) regions. The proposed model converts a signal slope into its effective fanout for delay estimation. Simulations show that for ISCAS benchmark circuits, our framework exhibits a speedup of three orders of magnitude over HSPICE with 5% error. Measured results in 65nm show that for a wide range of interconnect lengths and geometries, the proposed model predicts the circuit delay with 5.7% error at the supply voltage of VDD = 1.2V , and with 4.5% error at VDD = 0.4V .

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Slope interconnect effort: Gate-interconnect interdependentdelay model for CMOS logic gates

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