Software-based embedded core test using multi-polynomial for test data reduction

Soyeon Kang; Inhyuk Choi; Hyeonchan Lim; Sungyoul Seo; Sungho Kang

doi:10.1109/ISOCC.2016.7799762

Software-based embedded core test using multi-polynomial for test data reduction

Soyeon Kang, Inhyuk Choi, Hyeonchan Lim, Sungyoul Seo, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Software-based self-Test (SBST) is a self-Test where processors and intellectual property (IP) cores test itself using an embedded memory. However, an environment-limited memory size is one of the biggest challenges. In this paper, we present a new SBST solution using multiple polynomials. For reducing the required test data, the polynomials consist of a primitive polynomial and (BM)-Algorithm based polynomials and each polynomial generates pseudo random patterns and deterministic patterns respectively. Experimental results show that this SBST method reduces the size of the test program without a reduction of the fault coverage.

Original language	English
Title of host publication	ISOCC 2016 - International SoC Design Conference
Subtitle of host publication	Smart SoC for Intelligent Things
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	39-40
Number of pages	2
ISBN (Electronic)	9781467393089
DOIs	https://doi.org/10.1109/ISOCC.2016.7799762
Publication status	Published - 2016 Dec 27
Event	13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of Duration: 2016 Oct 23 → 2016 Oct 26

Publication series

Name	ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things

Other

Other	13th International SoC Design Conference, ISOCC 2016
Country/Territory	Korea, Republic of
City	Jeju
Period	16/10/23 → 16/10/26

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Instrumentation

Access to Document

10.1109/ISOCC.2016.7799762

Cite this

Kang, S., Choi, I., Lim, H., Seo, S., & Kang, S. (2016). Software-based embedded core test using multi-polynomial for test data reduction. In ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things (pp. 39-40). [7799762] (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2016.7799762

Kang, Soyeon ; Choi, Inhyuk ; Lim, Hyeonchan et al. / Software-based embedded core test using multi-polynomial for test data reduction. ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 39-40 (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things).

@inproceedings{18fce62cd7354c31bc792ce32117d42c,

title = "Software-based embedded core test using multi-polynomial for test data reduction",

abstract = "Software-based self-Test (SBST) is a self-Test where processors and intellectual property (IP) cores test itself using an embedded memory. However, an environment-limited memory size is one of the biggest challenges. In this paper, we present a new SBST solution using multiple polynomials. For reducing the required test data, the polynomials consist of a primitive polynomial and (BM)-Algorithm based polynomials and each polynomial generates pseudo random patterns and deterministic patterns respectively. Experimental results show that this SBST method reduces the size of the test program without a reduction of the fault coverage.",

author = "Soyeon Kang and Inhyuk Choi and Hyeonchan Lim and Sungyoul Seo and Sungho Kang",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 13th International SoC Design Conference, ISOCC 2016 ; Conference date: 23-10-2016 Through 26-10-2016",

year = "2016",

month = dec,

day = "27",

doi = "10.1109/ISOCC.2016.7799762",

language = "English",

series = "ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things",

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Kang, S, Choi, I, Lim, H, Seo, S & Kang, S 2016, Software-based embedded core test using multi-polynomial for test data reduction. in ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things., 7799762, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things, Institute of Electrical and Electronics Engineers Inc., pp. 39-40, 13th International SoC Design Conference, ISOCC 2016, Jeju, Korea, Republic of, 16/10/23. https://doi.org/10.1109/ISOCC.2016.7799762

Software-based embedded core test using multi-polynomial for test data reduction. / Kang, Soyeon; Choi, Inhyuk; Lim, Hyeonchan et al.

ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., 2016. p. 39-40 7799762 (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - Software-based self-Test (SBST) is a self-Test where processors and intellectual property (IP) cores test itself using an embedded memory. However, an environment-limited memory size is one of the biggest challenges. In this paper, we present a new SBST solution using multiple polynomials. For reducing the required test data, the polynomials consist of a primitive polynomial and (BM)-Algorithm based polynomials and each polynomial generates pseudo random patterns and deterministic patterns respectively. Experimental results show that this SBST method reduces the size of the test program without a reduction of the fault coverage.

AB - Software-based self-Test (SBST) is a self-Test where processors and intellectual property (IP) cores test itself using an embedded memory. However, an environment-limited memory size is one of the biggest challenges. In this paper, we present a new SBST solution using multiple polynomials. For reducing the required test data, the polynomials consist of a primitive polynomial and (BM)-Algorithm based polynomials and each polynomial generates pseudo random patterns and deterministic patterns respectively. Experimental results show that this SBST method reduces the size of the test program without a reduction of the fault coverage.

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Kang S, Choi I, Lim H, Seo S, Kang S. Software-based embedded core test using multi-polynomial for test data reduction. In ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc. 2016. p. 39-40. 7799762. (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things). doi: 10.1109/ISOCC.2016.7799762

Software-based embedded core test using multi-polynomial for test data reduction

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