Abstract
Software-based self-Test (SBST) is a self-Test where processors and intellectual property (IP) cores test itself using an embedded memory. However, an environment-limited memory size is one of the biggest challenges. In this paper, we present a new SBST solution using multiple polynomials. For reducing the required test data, the polynomials consist of a primitive polynomial and (BM)-Algorithm based polynomials and each polynomial generates pseudo random patterns and deterministic patterns respectively. Experimental results show that this SBST method reduces the size of the test program without a reduction of the fault coverage.
| Original language | English |
|---|---|
| Title of host publication | ISOCC 2016 - International SoC Design Conference |
| Subtitle of host publication | Smart SoC for Intelligent Things |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 39-40 |
| Number of pages | 2 |
| ISBN (Electronic) | 9781467393089 |
| DOIs | |
| Publication status | Published - 2016 Dec 27 |
| Event | 13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of Duration: 2016 Oct 23 → 2016 Oct 26 |
Publication series
| Name | ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things |
|---|
Other
| Other | 13th International SoC Design Conference, ISOCC 2016 |
|---|---|
| Country | Korea, Republic of |
| City | Jeju |
| Period | 16/10/23 → 16/10/26 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Instrumentation
Cite this
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Software-based embedded core test using multi-polynomial for test data reduction. / Kang, Soyeon; Choi, Inhyuk; Lim, Hyeonchan; Seo, Sungyoul; Kang, Sungho.
ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., 2016. p. 39-40 7799762 (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Software-based embedded core test using multi-polynomial for test data reduction
AU - Kang, Soyeon
AU - Choi, Inhyuk
AU - Lim, Hyeonchan
AU - Seo, Sungyoul
AU - Kang, Sungho
PY - 2016/12/27
Y1 - 2016/12/27
N2 - Software-based self-Test (SBST) is a self-Test where processors and intellectual property (IP) cores test itself using an embedded memory. However, an environment-limited memory size is one of the biggest challenges. In this paper, we present a new SBST solution using multiple polynomials. For reducing the required test data, the polynomials consist of a primitive polynomial and (BM)-Algorithm based polynomials and each polynomial generates pseudo random patterns and deterministic patterns respectively. Experimental results show that this SBST method reduces the size of the test program without a reduction of the fault coverage.
AB - Software-based self-Test (SBST) is a self-Test where processors and intellectual property (IP) cores test itself using an embedded memory. However, an environment-limited memory size is one of the biggest challenges. In this paper, we present a new SBST solution using multiple polynomials. For reducing the required test data, the polynomials consist of a primitive polynomial and (BM)-Algorithm based polynomials and each polynomial generates pseudo random patterns and deterministic patterns respectively. Experimental results show that this SBST method reduces the size of the test program without a reduction of the fault coverage.
UR - http://www.scopus.com/inward/record.url?scp=85010377940&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85010377940&partnerID=8YFLogxK
U2 - 10.1109/ISOCC.2016.7799762
DO - 10.1109/ISOCC.2016.7799762
M3 - Conference contribution
T3 - ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things
SP - 39
EP - 40
BT - ISOCC 2016 - International SoC Design Conference
PB - Institute of Electrical and Electronics Engineers Inc.
ER -