As technology scales down, an increasing number of transistors can be integrated into a single chip but process variation becomes more serious. SRAM is one of the key components in a SoC and it occupies a large portion of the SoC. Thus, the SRAM bitcell is typically designed using very small transistors for high integration, which limits the minimum operating voltage (V CCmin) of the SoC because of the large threshold voltage (V th) mismatch between paired transistors caused by small feature size. As process technology scales down to sub-32nm technology, the 6T SRAM bitcell that is currently used may not achieve proper stability, write-ability, and read-ability at the required operating voltage. In this paper, several approaches are investigated to resolve the issue, such as upsized 6T SRAM bitcell, 8T SRAM bitcell, read- and write-preferred bitcells, and read- and write-assist circuits. HSPICE simulations are performed using PTM 32nm model parameters.