This paper proposes a FinFET-based SRAM cell with data-aware power-gating write-assist to achieve both high read stability and write ability by using read-decoupled access transistors and power-gating PMOSs, respectively, for near-threshold operation. By adaptively cutting off the power-gating PMOS depending on the written data, the write disturbance from power supply can be eliminated, which facilitates more reliable write operation without any additional write assist circuit. Bit-interleaving scheme can be implemented in the proposed SRAM for soft error immunity while ensuring sufficient hold stability in half-selected cells during write operation. The proposed SRAM achieves read stability yield of 8.4σ and write ability yield of 6.1σ and consumes 0.47 pJ energy per operation at supply voltage of 0.4 V, a near-threshold voltage, in a 22-nm FinFET technology.
|Title of host publication||2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Publication status||Published - 2018 Apr 26|
|Event||2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy|
Duration: 2018 May 27 → 2018 May 30
|Name||Proceedings - IEEE International Symposium on Circuits and Systems|
|Other||2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018|
|Period||18/5/27 → 18/5/30|
Bibliographical notePublisher Copyright:
© 2018 IEEE.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering