SRAM Cell with Data-Aware Power-Gating Write-Asist for Near-Threshold Operation

Tae Woo Oh, Seong Ook Jung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper proposes a FinFET-based SRAM cell with data-aware power-gating write-assist to achieve both high read stability and write ability by using read-decoupled access transistors and power-gating PMOSs, respectively, for near-threshold operation. By adaptively cutting off the power-gating PMOS depending on the written data, the write disturbance from power supply can be eliminated, which facilitates more reliable write operation without any additional write assist circuit. Bit-interleaving scheme can be implemented in the proposed SRAM for soft error immunity while ensuring sufficient hold stability in half-selected cells during write operation. The proposed SRAM achieves read stability yield of 8.4σ and write ability yield of 6.1σ and consumes 0.47 pJ energy per operation at supply voltage of 0.4 V, a near-threshold voltage, in a 22-nm FinFET technology.

Original languageEnglish
Title of host publication2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538648810
DOIs
Publication statusPublished - 2018 Apr 26
Event2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy
Duration: 2018 May 272018 May 30

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2018-May
ISSN (Print)0271-4310

Other

Other2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
CountryItaly
CityFlorence
Period18/5/2718/5/30

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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