SRAM Design for 22-nm ETSOI technology: Selective cell current boosting and asymmetric back-gate write-assist circuit

As the semiconductor technology scales down, the read stability and write ability of a static random-access memory (SRAM) cell are degraded because of the increased mismatch among its transistors. Extremely thin silicon-on-insulator is one of the attractive candidates to reduce this mismatch, and it offers an independent back-gate control using a thin buried oxide. The implementation of back-gate control has recently attracted much interest to improve the read stability and write ability. In this paper, we propose a selective cell current (I_CELL) boosting scheme (SIB) and an asymmetric back-gate control write-assist (ABC-WA) circuit. SIB enhances the read performance by selectively boosting I_CELL of the SRAM cells. ABC-WA enhances the write ability by forward biasing the NMOSs at one side, which improves the write ability with reduction in the dynamic power overhead and without requiring a voltage generator. The proposed SRAM design improves the read performance and energy by 38.6% and 24.9%, respectively.