SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis

Tae Hoon Choi, Hanwool Jeong, Younghwi Yang, Juhyun Park, Seongook Jung

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

A static random access memory (SRAM) operational mismatch (SOMM) corner model and a methodology to efficiently estimate the SRAM read and write stability yield with the SOMM corner model are proposed. The proposed SOMM corner model effectively finds the combination of the transistor mismatch in SRAM, which represents the worst SRAM read or write operation in the given probabilistic distance (e.g., six sigma), and the SRAM yield can be estimated from the smallest probabilistic distance at which read or write operation failure occurs. With the proposed SOMM corner model implemented in the process design kit, the circuit designers can optimize the SRAM design by estimating the SRAM yield with significantly fewer computational resources, compared with the previous Monte Carlo-based methodologies. Numerical experiments show that the yield estimated by the proposed methodology matches well with the yield by Monte Carlo with importance sampling (error < 0.1 sigma); the simulation time takes less than 1 min, which is three orders of magnitude speedup over the conventional importance sampling methods.

Original languageEnglish
Article number7890466
Pages (from-to)2063-2072
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume64
Issue number8
DOIs
Publication statusPublished - 2017 Aug 1

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Data storage equipment
Networks (circuits)
Static random access storage
Importance sampling
Process design
Transistors
Experiments

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Choi, Tae Hoon ; Jeong, Hanwool ; Yang, Younghwi ; Park, Juhyun ; Jung, Seongook. / SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis. In: IEEE Transactions on Circuits and Systems I: Regular Papers. 2017 ; Vol. 64, No. 8. pp. 2063-2072.
@article{6d69f24dfa1c447085b62d3278392dda,
title = "SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis",
abstract = "A static random access memory (SRAM) operational mismatch (SOMM) corner model and a methodology to efficiently estimate the SRAM read and write stability yield with the SOMM corner model are proposed. The proposed SOMM corner model effectively finds the combination of the transistor mismatch in SRAM, which represents the worst SRAM read or write operation in the given probabilistic distance (e.g., six sigma), and the SRAM yield can be estimated from the smallest probabilistic distance at which read or write operation failure occurs. With the proposed SOMM corner model implemented in the process design kit, the circuit designers can optimize the SRAM design by estimating the SRAM yield with significantly fewer computational resources, compared with the previous Monte Carlo-based methodologies. Numerical experiments show that the yield estimated by the proposed methodology matches well with the yield by Monte Carlo with importance sampling (error < 0.1 sigma); the simulation time takes less than 1 min, which is three orders of magnitude speedup over the conventional importance sampling methods.",
author = "Choi, {Tae Hoon} and Hanwool Jeong and Younghwi Yang and Juhyun Park and Seongook Jung",
year = "2017",
month = "8",
day = "1",
doi = "10.1109/TCSI.2017.2685634",
language = "English",
volume = "64",
pages = "2063--2072",
journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",
issn = "1549-8328",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "8",

}

SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis. / Choi, Tae Hoon; Jeong, Hanwool; Yang, Younghwi; Park, Juhyun; Jung, Seongook.

In: IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 64, No. 8, 7890466, 01.08.2017, p. 2063-2072.

Research output: Contribution to journalArticle

TY - JOUR

T1 - SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis

AU - Choi, Tae Hoon

AU - Jeong, Hanwool

AU - Yang, Younghwi

AU - Park, Juhyun

AU - Jung, Seongook

PY - 2017/8/1

Y1 - 2017/8/1

N2 - A static random access memory (SRAM) operational mismatch (SOMM) corner model and a methodology to efficiently estimate the SRAM read and write stability yield with the SOMM corner model are proposed. The proposed SOMM corner model effectively finds the combination of the transistor mismatch in SRAM, which represents the worst SRAM read or write operation in the given probabilistic distance (e.g., six sigma), and the SRAM yield can be estimated from the smallest probabilistic distance at which read or write operation failure occurs. With the proposed SOMM corner model implemented in the process design kit, the circuit designers can optimize the SRAM design by estimating the SRAM yield with significantly fewer computational resources, compared with the previous Monte Carlo-based methodologies. Numerical experiments show that the yield estimated by the proposed methodology matches well with the yield by Monte Carlo with importance sampling (error < 0.1 sigma); the simulation time takes less than 1 min, which is three orders of magnitude speedup over the conventional importance sampling methods.

AB - A static random access memory (SRAM) operational mismatch (SOMM) corner model and a methodology to efficiently estimate the SRAM read and write stability yield with the SOMM corner model are proposed. The proposed SOMM corner model effectively finds the combination of the transistor mismatch in SRAM, which represents the worst SRAM read or write operation in the given probabilistic distance (e.g., six sigma), and the SRAM yield can be estimated from the smallest probabilistic distance at which read or write operation failure occurs. With the proposed SOMM corner model implemented in the process design kit, the circuit designers can optimize the SRAM design by estimating the SRAM yield with significantly fewer computational resources, compared with the previous Monte Carlo-based methodologies. Numerical experiments show that the yield estimated by the proposed methodology matches well with the yield by Monte Carlo with importance sampling (error < 0.1 sigma); the simulation time takes less than 1 min, which is three orders of magnitude speedup over the conventional importance sampling methods.

UR - http://www.scopus.com/inward/record.url?scp=85017110613&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85017110613&partnerID=8YFLogxK

U2 - 10.1109/TCSI.2017.2685634

DO - 10.1109/TCSI.2017.2685634

M3 - Article

VL - 64

SP - 2063

EP - 2072

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

SN - 1549-8328

IS - 8

M1 - 7890466

ER -