This paper presents SRAM write-and performance-assist cells that have bit-cell compatible layouts and thus can be inserted into an bit-cell array without the white space. The proposed cells can effectively resolve the degradation in write-ability and performance caused by the interconnect resistance increased with technology scaling.
|Title of host publication||2021 Symposium on VLSI Circuits, VLSI Circuits 2021|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Publication status||Published - 2021 Jun 13|
|Event||35th Symposium on VLSI Circuits, VLSI Circuits 2021 - Virutal, Online|
Duration: 2021 Jun 13 → 2021 Jun 19
|Name||IEEE Symposium on VLSI Circuits, Digest of Technical Papers|
|Conference||35th Symposium on VLSI Circuits, VLSI Circuits 2021|
|Period||21/6/13 → 21/6/19|
Bibliographical notePublisher Copyright:
© 2021 JSAP.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering