SST

A scalable parallel framework for architecture-level performance, power, area and thermal simulation

Ming Yu Hsieh, Rolf Riesen, Kevin Thompson, William Jinho Song, Arun Rodrigues

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

In this paper, we describe the integrated power, area and thermal modeling framework in the structural simulation toolkit (SST) for large-scale high performance computer simulation. It integrates various power and thermal modeling tools and computes run-time energy dissipation for core, network on chip, memory controller and shared cache. It also provides functionality to update the leakage power as temperature changes. We illustrate the utilization of the framework by applying it to explore interconnect options in manycore systems with consideration of temperature variation and leakage feedback. We compare power, energy-delay-area product (EDAP) and energy-delay product (EDP) of four manycore configurations-1 core, 2 cores, 4 cores and 8 cores per cluster. Results from simulation with or without consideration of temperature variation both show that the 4-core per cluster configuration has the best EDAP and EDP. Even so, considering that temperature variation increases total power dissipation, we demonstrate the importance of considering temperature variation in the design flow. With this power, area and thermal modeling capability, the SST can be used for hardware/software co-design of future exascale systems.

Original languageEnglish
Pages (from-to)181-191
Number of pages11
JournalComputer Journal
Volume55
Issue number2
DOIs
Publication statusPublished - 2012 Feb 1

Fingerprint

Energy dissipation
Temperature
Hot Temperature
Feedback
Hardware
Data storage equipment
Controllers
Computer simulation
Network-on-chip

All Science Journal Classification (ASJC) codes

  • Computer Science(all)

Cite this

Hsieh, Ming Yu ; Riesen, Rolf ; Thompson, Kevin ; Song, William Jinho ; Rodrigues, Arun. / SST : A scalable parallel framework for architecture-level performance, power, area and thermal simulation. In: Computer Journal. 2012 ; Vol. 55, No. 2. pp. 181-191.
@article{d75e9ee63eb841518ed452b66d9b4e0b,
title = "SST: A scalable parallel framework for architecture-level performance, power, area and thermal simulation",
abstract = "In this paper, we describe the integrated power, area and thermal modeling framework in the structural simulation toolkit (SST) for large-scale high performance computer simulation. It integrates various power and thermal modeling tools and computes run-time energy dissipation for core, network on chip, memory controller and shared cache. It also provides functionality to update the leakage power as temperature changes. We illustrate the utilization of the framework by applying it to explore interconnect options in manycore systems with consideration of temperature variation and leakage feedback. We compare power, energy-delay-area product (EDAP) and energy-delay product (EDP) of four manycore configurations-1 core, 2 cores, 4 cores and 8 cores per cluster. Results from simulation with or without consideration of temperature variation both show that the 4-core per cluster configuration has the best EDAP and EDP. Even so, considering that temperature variation increases total power dissipation, we demonstrate the importance of considering temperature variation in the design flow. With this power, area and thermal modeling capability, the SST can be used for hardware/software co-design of future exascale systems.",
author = "Hsieh, {Ming Yu} and Rolf Riesen and Kevin Thompson and Song, {William Jinho} and Arun Rodrigues",
year = "2012",
month = "2",
day = "1",
doi = "10.1093/comjnl/bxr069",
language = "English",
volume = "55",
pages = "181--191",
journal = "Computer Journal",
issn = "0010-4620",
publisher = "Oxford University Press",
number = "2",

}

SST : A scalable parallel framework for architecture-level performance, power, area and thermal simulation. / Hsieh, Ming Yu; Riesen, Rolf; Thompson, Kevin; Song, William Jinho; Rodrigues, Arun.

In: Computer Journal, Vol. 55, No. 2, 01.02.2012, p. 181-191.

Research output: Contribution to journalArticle

TY - JOUR

T1 - SST

T2 - A scalable parallel framework for architecture-level performance, power, area and thermal simulation

AU - Hsieh, Ming Yu

AU - Riesen, Rolf

AU - Thompson, Kevin

AU - Song, William Jinho

AU - Rodrigues, Arun

PY - 2012/2/1

Y1 - 2012/2/1

N2 - In this paper, we describe the integrated power, area and thermal modeling framework in the structural simulation toolkit (SST) for large-scale high performance computer simulation. It integrates various power and thermal modeling tools and computes run-time energy dissipation for core, network on chip, memory controller and shared cache. It also provides functionality to update the leakage power as temperature changes. We illustrate the utilization of the framework by applying it to explore interconnect options in manycore systems with consideration of temperature variation and leakage feedback. We compare power, energy-delay-area product (EDAP) and energy-delay product (EDP) of four manycore configurations-1 core, 2 cores, 4 cores and 8 cores per cluster. Results from simulation with or without consideration of temperature variation both show that the 4-core per cluster configuration has the best EDAP and EDP. Even so, considering that temperature variation increases total power dissipation, we demonstrate the importance of considering temperature variation in the design flow. With this power, area and thermal modeling capability, the SST can be used for hardware/software co-design of future exascale systems.

AB - In this paper, we describe the integrated power, area and thermal modeling framework in the structural simulation toolkit (SST) for large-scale high performance computer simulation. It integrates various power and thermal modeling tools and computes run-time energy dissipation for core, network on chip, memory controller and shared cache. It also provides functionality to update the leakage power as temperature changes. We illustrate the utilization of the framework by applying it to explore interconnect options in manycore systems with consideration of temperature variation and leakage feedback. We compare power, energy-delay-area product (EDAP) and energy-delay product (EDP) of four manycore configurations-1 core, 2 cores, 4 cores and 8 cores per cluster. Results from simulation with or without consideration of temperature variation both show that the 4-core per cluster configuration has the best EDAP and EDP. Even so, considering that temperature variation increases total power dissipation, we demonstrate the importance of considering temperature variation in the design flow. With this power, area and thermal modeling capability, the SST can be used for hardware/software co-design of future exascale systems.

UR - http://www.scopus.com/inward/record.url?scp=84856874372&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84856874372&partnerID=8YFLogxK

U2 - 10.1093/comjnl/bxr069

DO - 10.1093/comjnl/bxr069

M3 - Article

VL - 55

SP - 181

EP - 191

JO - Computer Journal

JF - Computer Journal

SN - 0010-4620

IS - 2

ER -