Static function prefetching for efficient code management on scratchpad memory

Youngbin Kim, Kyoungwoo Lee, Aviral Shrivastava

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As cache-based memory hierarchy is becoming a primary factor which limits the scalability and power efficiency of multi-core systems, scratchpad memory (SPM) has been studied as an alternative to cache. When SPM is used as an instruction memory, code management techniques are required to load code blocks on SPM using DMAs. In these techniques, code blocks are generally loaded on-demand to avoid loading incorrect block - unlike cache (e.g. tag arrays), SPM does not have mechanism to detect and recover from faults. While on-demand loading guarantees no fault, it leads to considerable performance overhead since it serializes the execution of DMA and CPU. This paper presents a technique to insert prefetching instructions for function-level code management to enable overlapping execution between DMA engine and CPU. Our technique inserts DMA instructions statically at compile time and does not rely on any profiling or run-time resources. Our evaluation shows that static prefetching can reduce CPU idle time due to DMAs by 58.5% and achieves 14.7% of average performance improvement on the benchmarks showing high overhead due to DMAs.

Original languageEnglish
Title of host publicationProceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages350-358
Number of pages9
ISBN (Electronic)9781538666487
DOIs
Publication statusPublished - 2019 Nov
Event37th IEEE International Conference on Computer Design, ICCD 2019 - Abu Dhabi, United Arab Emirates
Duration: 2019 Nov 172019 Nov 20

Publication series

NameProceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019

Conference

Conference37th IEEE International Conference on Computer Design, ICCD 2019
Country/TerritoryUnited Arab Emirates
CityAbu Dhabi
Period19/11/1719/11/20

Bibliographical note

Funding Information:
ACKNOWLEDGEMENTS This work was partially supported by Institute of Information & Communications Technology Planning & Evaluation (IITP) grant funded by the Korea government (MSIT) (No. 2014-3-00035, Research on High Performance and Scalable Manycore Operating System) and by NRF-2015M3C4A7065522 (Next-generation Information Computing Development Program, NRF, MSIT).

Publisher Copyright:
© 2019 IEEE.

All Science Journal Classification (ASJC) codes

  • Information Systems and Management
  • Computer Networks and Communications
  • Control and Optimization
  • Hardware and Architecture

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