As cache-based memory hierarchy is becoming a primary factor which limits the scalability and power efficiency of multi-core systems, scratchpad memory (SPM) has been studied as an alternative to cache. When SPM is used as an instruction memory, code management techniques are required to load code blocks on SPM using DMAs. In these techniques, code blocks are generally loaded on-demand to avoid loading incorrect block - unlike cache (e.g. tag arrays), SPM does not have mechanism to detect and recover from faults. While on-demand loading guarantees no fault, it leads to considerable performance overhead since it serializes the execution of DMA and CPU. This paper presents a technique to insert prefetching instructions for function-level code management to enable overlapping execution between DMA engine and CPU. Our technique inserts DMA instructions statically at compile time and does not rely on any profiling or run-time resources. Our evaluation shows that static prefetching can reduce CPU idle time due to DMAs by 58.5% and achieves 14.7% of average performance improvement on the benchmarks showing high overhead due to DMAs.
|Title of host publication||Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||9|
|Publication status||Published - 2019 Nov|
|Event||37th IEEE International Conference on Computer Design, ICCD 2019 - Abu Dhabi, United Arab Emirates|
Duration: 2019 Nov 17 → 2019 Nov 20
|Name||Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019|
|Conference||37th IEEE International Conference on Computer Design, ICCD 2019|
|Country/Territory||United Arab Emirates|
|Period||19/11/17 → 19/11/20|
Bibliographical noteFunding Information:
ACKNOWLEDGEMENTS This work was partially supported by Institute of Information & Communications Technology Planning & Evaluation (IITP) grant funded by the Korea government (MSIT) (No. 2014-3-00035, Research on High Performance and Scalable Manycore Operating System) and by NRF-2015M3C4A7065522 (Next-generation Information Computing Development Program, NRF, MSIT).
© 2019 IEEE.
All Science Journal Classification (ASJC) codes
- Information Systems and Management
- Computer Networks and Communications
- Control and Optimization
- Hardware and Architecture