A new statistical simulation methodology under process variations in deep sub-micron technology is described. By dividing the overall memory system into sub-blocks and running Monte Carlo simulations locally, significant reduction in the statistical simulation time is achieved. A novel methodology to combine the simulation results and accurately predict the read access failure of the overall system is also presented. This allows allocation of design margins and setting of design guidelines for each sub-block in the early design stage.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering