Symmetrical dense disparity estimation: Algorithms and FPGAs implementation

In this paper, we propose new algorithms of window-based disparity estimation- 'bi-level window refinement' and 'Symmetrical Search', and modify conventional fast algorithm- 'Partial Sum Approach'. With these algorithms, we can achieve 1600MDPS with implementing to FPGAs using 10% of FPGAs area, and it can generate dense disparity map which has size of maximum 1024 by 1024 and frame rate of 47 frames per second. It is 20 times as fast as the disparity estimator used in these days. Our disparity map is smooth in planar area, but detail in discontinuous area. In this paper, we will show the process for implementation and compare the result with conventional algorithms for hardware, as well as complicate algorithms for software. We have confirmed the proper qualitative performance for IVR in processing the experiments in the end.