3D stacked memory has significant advantages in terms of high bandwidth, high density, low latency, low power consumption and etc. In 3D architecture, the reliability of each memory layer varies with respect to its working environment. Previous studies have introduced various ways to improve the reliability of upper dies against soft errors, and examined the enhanced memory bit-error-rate (BER) tolerability. However, to the best of our knowledge, there has been few or no system-level analysis of the effects of the bit error in 3D memory. In this paper, we examine system-level failure rates in a wide range of BER. In addition, by utilizing the difference of impact between instruction bit error and data bit error, we propose a simple memory allocation scheme in 3D memory. Simulation results shows the proposed memory allocation scheme can be effectively adopted to 3D memory.