System-level failure simulation and memory allocation scheme in 3D memory

Jung Jin Lee; Joon Sung Yang

doi:10.1109/APCCAS.2016.7804062

System-level failure simulation and memory allocation scheme in 3D memory

Jung Jin Lee, Joon Sung Yang

College of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

3D stacked memory has significant advantages in terms of high bandwidth, high density, low latency, low power consumption and etc. In 3D architecture, the reliability of each memory layer varies with respect to its working environment. Previous studies have introduced various ways to improve the reliability of upper dies against soft errors, and examined the enhanced memory bit-error-rate (BER) tolerability. However, to the best of our knowledge, there has been few or no system-level analysis of the effects of the bit error in 3D memory. In this paper, we examine system-level failure rates in a wide range of BER. In addition, by utilizing the difference of impact between instruction bit error and data bit error, we propose a simple memory allocation scheme in 3D memory. Simulation results shows the proposed memory allocation scheme can be effectively adopted to 3D memory.

Original language	English
Title of host publication	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	674-675
Number of pages	2
ISBN (Electronic)	9781509015702
DOIs	https://doi.org/10.1109/APCCAS.2016.7804062
Publication status	Published - 2017 Jan 3
Event	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 - Jeju, Korea, Republic of Duration: 2016 Oct 25 → 2016 Oct 28

Publication series

Name	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016

Other

Other	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
Country	Korea, Republic of
City	Jeju
Period	16/10/25 → 16/10/28

Bibliographical note

Funding Information:
This work was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (NRF-2015R1D1A1A01058856)

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Signal Processing

Access to Document

10.1109/APCCAS.2016.7804062

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Lee, J. J., & Yang, J. S. (2017). System-level failure simulation and memory allocation scheme in 3D memory. In 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 (pp. 674-675). [7804062] (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2016.7804062

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abstract = "3D stacked memory has significant advantages in terms of high bandwidth, high density, low latency, low power consumption and etc. In 3D architecture, the reliability of each memory layer varies with respect to its working environment. Previous studies have introduced various ways to improve the reliability of upper dies against soft errors, and examined the enhanced memory bit-error-rate (BER) tolerability. However, to the best of our knowledge, there has been few or no system-level analysis of the effects of the bit error in 3D memory. In this paper, we examine system-level failure rates in a wide range of BER. In addition, by utilizing the difference of impact between instruction bit error and data bit error, we propose a simple memory allocation scheme in 3D memory. Simulation results shows the proposed memory allocation scheme can be effectively adopted to 3D memory.",

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note = "Funding Information: This work was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (NRF-2015R1D1A1A01058856); 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 ; Conference date: 25-10-2016 Through 28-10-2016",

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Lee, JJ & Yang, JS 2017, System-level failure simulation and memory allocation scheme in 3D memory. in 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016., 7804062, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Institute of Electrical and Electronics Engineers Inc., pp. 674-675, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Jeju, Korea, Republic of, 16/10/25. https://doi.org/10.1109/APCCAS.2016.7804062

System-level failure simulation and memory allocation scheme in 3D memory. / Lee, Jung Jin; Yang, Joon Sung.

2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., 2017. p. 674-675 7804062 (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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