System-level failure simulation and memory allocation scheme in 3D memory

Jung Jin Lee, Joon Sung Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

3D stacked memory has significant advantages in terms of high bandwidth, high density, low latency, low power consumption and etc. In 3D architecture, the reliability of each memory layer varies with respect to its working environment. Previous studies have introduced various ways to improve the reliability of upper dies against soft errors, and examined the enhanced memory bit-error-rate (BER) tolerability. However, to the best of our knowledge, there has been few or no system-level analysis of the effects of the bit error in 3D memory. In this paper, we examine system-level failure rates in a wide range of BER. In addition, by utilizing the difference of impact between instruction bit error and data bit error, we propose a simple memory allocation scheme in 3D memory. Simulation results shows the proposed memory allocation scheme can be effectively adopted to 3D memory.

Original languageEnglish
Title of host publication2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages674-675
Number of pages2
ISBN (Electronic)9781509015702
DOIs
Publication statusPublished - 2017 Jan 3
Event2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 - Jeju, Korea, Republic of
Duration: 2016 Oct 252016 Oct 28

Publication series

Name2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016

Other

Other2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
CountryKorea, Republic of
CityJeju
Period16/10/2516/10/28

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Signal Processing

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  • Cite this

    Lee, J. J., & Yang, J. S. (2017). System-level failure simulation and memory allocation scheme in 3D memory. In 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 (pp. 674-675). [7804062] (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2016.7804062