The era of the Internet of Things (IoT) is upon us. In this era, minimizing power consumption becomes a primary concern of system-on-chip designers. Ultralow power (ULP) very large-scale integration circuits have been receiving considerable interest from both academia and industry as the best-suited techniques for IoT devices, which can take full advantage of power-saving that voltage scaling potentially achieves. Consequently, research on ULP designs has begun to yield tangible outcomes, namely ULP circuits. However, little attention has been paid to ULP network-on-chip (NoC), although the NoC is an essential of the ULP chips, and its power consumption accounts for a significant portion of the total power. This paper focuses on ULP NoCs, and presents a new power management method that exploits delay versus temperature characteristics of ULP circuits. Recent studies on ULP circuits show that delay versus temperature characteristics are fundamentally different from normal circuits, i.e., the delay of the ULP circuits implemented in state-of-the-art bulk CMOS operating at low supply voltages or in FinFET technologies decreases with increasing temperature, a phenomenon known as the temperature effect inversion (TEI). Starting with an intuition that at a certain temperature point, power savings without performance penalty can be achieved by increasing the router frequency to create the opportunity to turn off some routers in ULP NoCs, or by decreasing the NoC supply voltage level, an optimization method is presented to maximize the power savings with minor performance penalty. To validate the proposed method, a concrete ULP NoC simulator, TEI-Noxim, has been developed. Experimental results demonstrate that TEI-aware NoC achieves an average of 36.0% power reduction over 21 applications.
|Number of pages||14|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|Publication status||Published - 2018 Feb|
Bibliographical noteFunding Information:
Manuscript received July 14, 2016; revised November 2, 2016 and February 6, 2017; accepted March 21, 2017. Date of publication April 12, 2017; date of current version January 19, 2018. This work was supported in part by the IT Research and Development Program of MSIP/KEIT under Grant 2016-0-00088 (Development of Intelligent Semiconductor Common Platform Technology for Smart Devices), and in part by the U.S. National Science Foundation through the Software and Hardware Foundations Program. This paper was recommended by Associate Editor J. Xu. (Corresponding author: Woojoo Lee.) K. Han and J.-J. Lee are with Electronics and Telecommunications Research Institute, Daejeon 34129, South Korea (e-mail: firstname.lastname@example.org; email@example.com).
© 2017 IEEE.
All Science Journal Classification (ASJC) codes
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering