Test access mechaism for stack test time reduction of 3-dimensional integrated circuit

Inhyuk Choi, Hyunggoy Oh, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, the reconfigurable test access mechanism (RTAM) is designed based on the emerging test standard to reduce the cumulative stack test time of the 3-dimensional integrated circuit (3-D IC). The RTAM enables the test scheduling to reflect the variation of the test constraints in the overall stack test phases. Simulation results show the RTAM achieves the cumulative stack test time reduction compared with a non-reconfigurable TAM for the stacked dies in the 3-D IC.

Original languageEnglish
Title of host publication2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages522-525
Number of pages4
ISBN (Electronic)9781509015702
DOIs
Publication statusPublished - 2017 Jan 3
Event2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 - Jeju, Korea, Republic of
Duration: 2016 Oct 252016 Oct 28

Publication series

Name2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016

Other

Other2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
CountryKorea, Republic of
CityJeju
Period16/10/2516/10/28

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Signal Processing

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    Choi, I., Oh, H., & Kang, S. (2017). Test access mechaism for stack test time reduction of 3-dimensional integrated circuit. In 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 (pp. 522-525). [7804019] (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2016.7804019