Test data reduction method based on berlekamp-massey algorithm

Hyeonchan Lim; Junghwan Kim; Soyeon Kang; Sungho Kang

doi:10.1109/ISOCC.2017.8368800

Test data reduction method based on berlekamp-massey algorithm

Hyeonchan Lim, Junghwan Kim, Soyeon Kang, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

Due to innovation of manufacturing technology of integrated circuit (IC), more transistors have been integrated on a single IC, which makes the volume of test data become one of major factors of testing system-on-chips (SoCs). As the large volume of test data is contributed to increased test cost (including test time, tester memory requirement, power consuming), test data reduction and generation method based on berlekamp-massey (BM) algorithm is proposed to reduce the volume of test data. The proposed method reduces test data by exploiting compatibility among scan flip-flops (SFFs) and using LFSRs which are synthesized by BM algorithm. The compatible SFFs are combined into a group and are broadcasted from the same LFSR. The test data which are broadcasted from the LFSR are compressed into seeds which are results of BM algorithm. The proposed method is verified by ISCAS'89 benchmark circuits and the experimental results shows that the compression ratio is up to 10X that implies test application time (TAT) is also reduced.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2017, ISOCC 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	123-124
Number of pages	2
ISBN (Electronic)	9781538622858
DOIs	https://doi.org/10.1109/ISOCC.2017.8368800
Publication status	Published - 2018 May 29
Event	14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of Duration: 2017 Nov 5 → 2017 Nov 8

Publication series

Name	Proceedings - International SoC Design Conference 2017, ISOCC 2017

Other

Other	14th International SoC Design Conference, ISOCC 2017
Country/Territory	Korea, Republic of
City	Seoul
Period	17/11/5 → 17/11/8

Bibliographical note

Funding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government(MSIP) (No. 2015R1A2A1A13001751).

Publisher Copyright:
© 2017 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ISOCC.2017.8368800

Cite this

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title = "Test data reduction method based on berlekamp-massey algorithm",

abstract = "Due to innovation of manufacturing technology of integrated circuit (IC), more transistors have been integrated on a single IC, which makes the volume of test data become one of major factors of testing system-on-chips (SoCs). As the large volume of test data is contributed to increased test cost (including test time, tester memory requirement, power consuming), test data reduction and generation method based on berlekamp-massey (BM) algorithm is proposed to reduce the volume of test data. The proposed method reduces test data by exploiting compatibility among scan flip-flops (SFFs) and using LFSRs which are synthesized by BM algorithm. The compatible SFFs are combined into a group and are broadcasted from the same LFSR. The test data which are broadcasted from the LFSR are compressed into seeds which are results of BM algorithm. The proposed method is verified by ISCAS'89 benchmark circuits and the experimental results shows that the compression ratio is up to 10X that implies test application time (TAT) is also reduced.",

author = "Hyeonchan Lim and Junghwan Kim and Soyeon Kang and Sungho Kang",

note = "Funding Information: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government(MSIP) (No. 2015R1A2A1A13001751). Publisher Copyright: {\textcopyright} 2017 IEEE.; 14th International SoC Design Conference, ISOCC 2017 ; Conference date: 05-11-2017 Through 08-11-2017",

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doi = "10.1109/ISOCC.2017.8368800",

language = "English",

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Lim, H, Kim, J, Kang, S & Kang, S 2018, Test data reduction method based on berlekamp-massey algorithm. in Proceedings - International SoC Design Conference 2017, ISOCC 2017. Proceedings - International SoC Design Conference 2017, ISOCC 2017, Institute of Electrical and Electronics Engineers Inc., pp. 123-124, 14th International SoC Design Conference, ISOCC 2017, Seoul, Korea, Republic of, 17/11/5. https://doi.org/10.1109/ISOCC.2017.8368800

Test data reduction method based on berlekamp-massey algorithm. / Lim, Hyeonchan; Kim, Junghwan; Kang, Soyeon et al.

Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 123-124 (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Kim, Junghwan

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AU - Kang, Sungho

N1 - Funding Information: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government(MSIP) (No. 2015R1A2A1A13001751). Publisher Copyright: © 2017 IEEE.

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Y1 - 2018/5/29

N2 - Due to innovation of manufacturing technology of integrated circuit (IC), more transistors have been integrated on a single IC, which makes the volume of test data become one of major factors of testing system-on-chips (SoCs). As the large volume of test data is contributed to increased test cost (including test time, tester memory requirement, power consuming), test data reduction and generation method based on berlekamp-massey (BM) algorithm is proposed to reduce the volume of test data. The proposed method reduces test data by exploiting compatibility among scan flip-flops (SFFs) and using LFSRs which are synthesized by BM algorithm. The compatible SFFs are combined into a group and are broadcasted from the same LFSR. The test data which are broadcasted from the LFSR are compressed into seeds which are results of BM algorithm. The proposed method is verified by ISCAS'89 benchmark circuits and the experimental results shows that the compression ratio is up to 10X that implies test application time (TAT) is also reduced.

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ER -

Test data reduction method based on berlekamp-massey algorithm

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