Abstract
Due to innovation of manufacturing technology of integrated circuit (IC), more transistors have been integrated on a single IC, which makes the volume of test data become one of major factors of testing system-on-chips (SoCs). As the large volume of test data is contributed to increased test cost (including test time, tester memory requirement, power consuming), test data reduction and generation method based on berlekamp-massey (BM) algorithm is proposed to reduce the volume of test data. The proposed method reduces test data by exploiting compatibility among scan flip-flops (SFFs) and using LFSRs which are synthesized by BM algorithm. The compatible SFFs are combined into a group and are broadcasted from the same LFSR. The test data which are broadcasted from the LFSR are compressed into seeds which are results of BM algorithm. The proposed method is verified by ISCAS'89 benchmark circuits and the experimental results shows that the compression ratio is up to 10X that implies test application time (TAT) is also reduced.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - International SoC Design Conference 2017, ISOCC 2017 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 123-124 |
| Number of pages | 2 |
| ISBN (Electronic) | 9781538622858 |
| DOIs | |
| Publication status | Published - 2018 May 29 |
| Event | 14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of Duration: 2017 Nov 5 → 2017 Nov 8 |
Publication series
| Name | Proceedings - International SoC Design Conference 2017, ISOCC 2017 |
|---|
Other
| Other | 14th International SoC Design Conference, ISOCC 2017 |
|---|---|
| Country | Korea, Republic of |
| City | Seoul |
| Period | 17/11/5 → 17/11/8 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
Cite this
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Test data reduction method based on berlekamp-massey algorithm. / Lim, Hyeonchan; Kim, Junghwan; Kang, Soyeon; Kang, Sungho.
Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 123-124 (Proceedings - International SoC Design Conference 2017, ISOCC 2017).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Test data reduction method based on berlekamp-massey algorithm
AU - Lim, Hyeonchan
AU - Kim, Junghwan
AU - Kang, Soyeon
AU - Kang, Sungho
PY - 2018/5/29
Y1 - 2018/5/29
N2 - Due to innovation of manufacturing technology of integrated circuit (IC), more transistors have been integrated on a single IC, which makes the volume of test data become one of major factors of testing system-on-chips (SoCs). As the large volume of test data is contributed to increased test cost (including test time, tester memory requirement, power consuming), test data reduction and generation method based on berlekamp-massey (BM) algorithm is proposed to reduce the volume of test data. The proposed method reduces test data by exploiting compatibility among scan flip-flops (SFFs) and using LFSRs which are synthesized by BM algorithm. The compatible SFFs are combined into a group and are broadcasted from the same LFSR. The test data which are broadcasted from the LFSR are compressed into seeds which are results of BM algorithm. The proposed method is verified by ISCAS'89 benchmark circuits and the experimental results shows that the compression ratio is up to 10X that implies test application time (TAT) is also reduced.
AB - Due to innovation of manufacturing technology of integrated circuit (IC), more transistors have been integrated on a single IC, which makes the volume of test data become one of major factors of testing system-on-chips (SoCs). As the large volume of test data is contributed to increased test cost (including test time, tester memory requirement, power consuming), test data reduction and generation method based on berlekamp-massey (BM) algorithm is proposed to reduce the volume of test data. The proposed method reduces test data by exploiting compatibility among scan flip-flops (SFFs) and using LFSRs which are synthesized by BM algorithm. The compatible SFFs are combined into a group and are broadcasted from the same LFSR. The test data which are broadcasted from the LFSR are compressed into seeds which are results of BM algorithm. The proposed method is verified by ISCAS'89 benchmark circuits and the experimental results shows that the compression ratio is up to 10X that implies test application time (TAT) is also reduced.
UR - http://www.scopus.com/inward/record.url?scp=85048859551&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85048859551&partnerID=8YFLogxK
U2 - 10.1109/ISOCC.2017.8368800
DO - 10.1109/ISOCC.2017.8368800
M3 - Conference contribution
AN - SCOPUS:85048859551
T3 - Proceedings - International SoC Design Conference 2017, ISOCC 2017
SP - 123
EP - 124
BT - Proceedings - International SoC Design Conference 2017, ISOCC 2017
PB - Institute of Electrical and Electronics Engineers Inc.
ER -