Test data reduction method based on berlekamp-massey algorithm

Due to innovation of manufacturing technology of integrated circuit (IC), more transistors have been integrated on a single IC, which makes the volume of test data become one of major factors of testing system-on-chips (SoCs). As the large volume of test data is contributed to increased test cost (including test time, tester memory requirement, power consuming), test data reduction and generation method based on berlekamp-massey (BM) algorithm is proposed to reduce the volume of test data. The proposed method reduces test data by exploiting compatibility among scan flip-flops (SFFs) and using LFSRs which are synthesized by BM algorithm. The compatible SFFs are combined into a group and are broadcasted from the same LFSR. The test data which are broadcasted from the LFSR are compressed into seeds which are results of BM algorithm. The proposed method is verified by ISCAS'89 benchmark circuits and the experimental results shows that the compression ratio is up to 10X that implies test application time (TAT) is also reduced.