Abstract
A new test-decompression methodology using a variable-rank multiple-polynomial linear feedback shift register (MP-LFSR) is proposed. In the proposed reseeding scheme, a test cube with a large number of specified bits is encoded with a high-rank polynomial, while a test cube with a small number of specified bits is encoded with a low-rank polynomial. Therefore, according to the number of specified bits in each test cube, the size of the encoded data can be optimally reduced. A variable-rank MP-LFSR can be implemented with a slight modification of a conventional MP-LFSR. The experimental results on the largest ISCAS'89 benchmark circuits show that the proposed methodology can provide much better encoding efficiency than the previous methods with adequate hardware overhead.
| Original language | English |
|---|---|
| Pages (from-to) | 687-690 |
| Number of pages | 4 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 11 |
| Issue number | 4 |
| DOIs | |
| Publication status | Published - 2003 Aug 1 |
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All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering
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Test-Decompression Mechanism Using a Variable-Length Multiple-Polynomial LFSR. / Kim, Hong Sik; Kim, Yongjoon; Kang, Sungho.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 11, No. 4, 01.08.2003, p. 687-690.Research output: Contribution to journal › Article
TY - JOUR
T1 - Test-Decompression Mechanism Using a Variable-Length Multiple-Polynomial LFSR
AU - Kim, Hong Sik
AU - Kim, Yongjoon
AU - Kang, Sungho
PY - 2003/8/1
Y1 - 2003/8/1
N2 - A new test-decompression methodology using a variable-rank multiple-polynomial linear feedback shift register (MP-LFSR) is proposed. In the proposed reseeding scheme, a test cube with a large number of specified bits is encoded with a high-rank polynomial, while a test cube with a small number of specified bits is encoded with a low-rank polynomial. Therefore, according to the number of specified bits in each test cube, the size of the encoded data can be optimally reduced. A variable-rank MP-LFSR can be implemented with a slight modification of a conventional MP-LFSR. The experimental results on the largest ISCAS'89 benchmark circuits show that the proposed methodology can provide much better encoding efficiency than the previous methods with adequate hardware overhead.
AB - A new test-decompression methodology using a variable-rank multiple-polynomial linear feedback shift register (MP-LFSR) is proposed. In the proposed reseeding scheme, a test cube with a large number of specified bits is encoded with a high-rank polynomial, while a test cube with a small number of specified bits is encoded with a low-rank polynomial. Therefore, according to the number of specified bits in each test cube, the size of the encoded data can be optimally reduced. A variable-rank MP-LFSR can be implemented with a slight modification of a conventional MP-LFSR. The experimental results on the largest ISCAS'89 benchmark circuits show that the proposed methodology can provide much better encoding efficiency than the previous methods with adequate hardware overhead.
UR - http://www.scopus.com/inward/record.url?scp=0141527464&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0141527464&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2003.812287
DO - 10.1109/TVLSI.2003.812287
M3 - Article
VL - 11
SP - 687
EP - 690
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 4
ER -