Test item priority estimation for high parallel test efficiency under ATE debug time constraints

Young Woo Lee, Inhyuk Choi, Kang Hoon Oh, James Jinsoo Ko, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Semiconductor manufacture companies make an effort to reduce the test time for the test cost reduction until mass production starts. One of the effective test time reduction techniques is to improve the parallel test efficiency with the test program optimization by debugging on the automatic test equipment (ATE). However, given the time constraints of production schedules, the available time for the test program optimization is not enough to debug all test items at all. For this reason, it is important to select cost-effective test items in order to optimize the test program for the test time reduction. In this paper, we introduce the test item priority estimation method for high parallel test efficiency. Experimental results obtained from the actual industrial system-on-chip (SoC) circuits show that our proposed method provides the lower total test time for mass production under the same ATE debug time constraints as the cost-effective solution.

Original languageEnglish
Title of host publicationITC-Asia 2017 - International Test Conference in Asia
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages150-154
Number of pages5
ISBN (Electronic)9781538630518
DOIs
Publication statusPublished - 2017 Nov 3
Event1st International Test Conference in Asia, ITC-Asia 2017 - Taipei, Taiwan, Province of China
Duration: 2017 Sep 132017 Sep 15

Publication series

NameITC-Asia 2017 - International Test Conference in Asia

Conference

Conference1st International Test Conference in Asia, ITC-Asia 2017
CountryTaiwan, Province of China
CityTaipei
Period17/9/1317/9/15

Fingerprint

Cost reduction
Costs
Semiconductor materials
Networks (circuits)
Industry
System-on-chip

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Automotive Engineering
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Lee, Y. W., Choi, I., Oh, K. H., Ko, J. J., & Kang, S. (2017). Test item priority estimation for high parallel test efficiency under ATE debug time constraints. In ITC-Asia 2017 - International Test Conference in Asia (pp. 150-154). [8097131] (ITC-Asia 2017 - International Test Conference in Asia). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ITC-ASIA.2017.8097131
Lee, Young Woo ; Choi, Inhyuk ; Oh, Kang Hoon ; Ko, James Jinsoo ; Kang, Sungho. / Test item priority estimation for high parallel test efficiency under ATE debug time constraints. ITC-Asia 2017 - International Test Conference in Asia. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 150-154 (ITC-Asia 2017 - International Test Conference in Asia).
@inproceedings{d3d6af1254894f27a8b0db6041368d2b,
title = "Test item priority estimation for high parallel test efficiency under ATE debug time constraints",
abstract = "Semiconductor manufacture companies make an effort to reduce the test time for the test cost reduction until mass production starts. One of the effective test time reduction techniques is to improve the parallel test efficiency with the test program optimization by debugging on the automatic test equipment (ATE). However, given the time constraints of production schedules, the available time for the test program optimization is not enough to debug all test items at all. For this reason, it is important to select cost-effective test items in order to optimize the test program for the test time reduction. In this paper, we introduce the test item priority estimation method for high parallel test efficiency. Experimental results obtained from the actual industrial system-on-chip (SoC) circuits show that our proposed method provides the lower total test time for mass production under the same ATE debug time constraints as the cost-effective solution.",
author = "Lee, {Young Woo} and Inhyuk Choi and Oh, {Kang Hoon} and Ko, {James Jinsoo} and Sungho Kang",
year = "2017",
month = "11",
day = "3",
doi = "10.1109/ITC-ASIA.2017.8097131",
language = "English",
series = "ITC-Asia 2017 - International Test Conference in Asia",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "150--154",
booktitle = "ITC-Asia 2017 - International Test Conference in Asia",
address = "United States",

}

Lee, YW, Choi, I, Oh, KH, Ko, JJ & Kang, S 2017, Test item priority estimation for high parallel test efficiency under ATE debug time constraints. in ITC-Asia 2017 - International Test Conference in Asia., 8097131, ITC-Asia 2017 - International Test Conference in Asia, Institute of Electrical and Electronics Engineers Inc., pp. 150-154, 1st International Test Conference in Asia, ITC-Asia 2017, Taipei, Taiwan, Province of China, 17/9/13. https://doi.org/10.1109/ITC-ASIA.2017.8097131

Test item priority estimation for high parallel test efficiency under ATE debug time constraints. / Lee, Young Woo; Choi, Inhyuk; Oh, Kang Hoon; Ko, James Jinsoo; Kang, Sungho.

ITC-Asia 2017 - International Test Conference in Asia. Institute of Electrical and Electronics Engineers Inc., 2017. p. 150-154 8097131 (ITC-Asia 2017 - International Test Conference in Asia).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Test item priority estimation for high parallel test efficiency under ATE debug time constraints

AU - Lee, Young Woo

AU - Choi, Inhyuk

AU - Oh, Kang Hoon

AU - Ko, James Jinsoo

AU - Kang, Sungho

PY - 2017/11/3

Y1 - 2017/11/3

N2 - Semiconductor manufacture companies make an effort to reduce the test time for the test cost reduction until mass production starts. One of the effective test time reduction techniques is to improve the parallel test efficiency with the test program optimization by debugging on the automatic test equipment (ATE). However, given the time constraints of production schedules, the available time for the test program optimization is not enough to debug all test items at all. For this reason, it is important to select cost-effective test items in order to optimize the test program for the test time reduction. In this paper, we introduce the test item priority estimation method for high parallel test efficiency. Experimental results obtained from the actual industrial system-on-chip (SoC) circuits show that our proposed method provides the lower total test time for mass production under the same ATE debug time constraints as the cost-effective solution.

AB - Semiconductor manufacture companies make an effort to reduce the test time for the test cost reduction until mass production starts. One of the effective test time reduction techniques is to improve the parallel test efficiency with the test program optimization by debugging on the automatic test equipment (ATE). However, given the time constraints of production schedules, the available time for the test program optimization is not enough to debug all test items at all. For this reason, it is important to select cost-effective test items in order to optimize the test program for the test time reduction. In this paper, we introduce the test item priority estimation method for high parallel test efficiency. Experimental results obtained from the actual industrial system-on-chip (SoC) circuits show that our proposed method provides the lower total test time for mass production under the same ATE debug time constraints as the cost-effective solution.

UR - http://www.scopus.com/inward/record.url?scp=85040615236&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85040615236&partnerID=8YFLogxK

U2 - 10.1109/ITC-ASIA.2017.8097131

DO - 10.1109/ITC-ASIA.2017.8097131

M3 - Conference contribution

AN - SCOPUS:85040615236

T3 - ITC-Asia 2017 - International Test Conference in Asia

SP - 150

EP - 154

BT - ITC-Asia 2017 - International Test Conference in Asia

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Lee YW, Choi I, Oh KH, Ko JJ, Kang S. Test item priority estimation for high parallel test efficiency under ATE debug time constraints. In ITC-Asia 2017 - International Test Conference in Asia. Institute of Electrical and Electronics Engineers Inc. 2017. p. 150-154. 8097131. (ITC-Asia 2017 - International Test Conference in Asia). https://doi.org/10.1109/ITC-ASIA.2017.8097131