Test methodology for low power SRAM's (Is Iddq test useful for low power SRAM's?)

Ilseok Suh, Hong Sik Kim, Sungho Kang, Gunhee Han

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The increase in integrity of the recent VLSI technology has enabled a trend of small and portable applications. These portable applications, like notebook computers and cellular phones, need the high-performance and low-power consumption. In most products the major power consuming elements are the memories. So low power memory technology has been developed. But the test features have not been studied sufficiently. This paper provides a test methodology useful for low power SRAM's. Also simulation results for the Driving Source Line technology show how useful the Iddq test is.

Original languageEnglish
Title of host publicationProceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages277-280
Number of pages4
ISBN (Electronic)0780364708, 9780780364707
DOIs
Publication statusPublished - 2000 Jan 1
Event2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000 - Cheju, Korea, Republic of
Duration: 2000 Aug 282000 Aug 30

Publication series

NameProceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000

Other

Other2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000
CountryKorea, Republic of
CityCheju
Period00/8/2800/8/30

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All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Suh, I., Kim, H. S., Kang, S., & Han, G. (2000). Test methodology for low power SRAM's (Is Iddq test useful for low power SRAM's?). In Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000 (pp. 277-280). [896962] (Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APASIC.2000.896962