BIST (built-in self test) is one of the most attractive solutions to test chips at speed. In this paper, we present a new test pattern generation method using the processing units of DSP (digital signal processing). This method utilizes dual MAC (multiply and accumulate) units, which consist of two multipliers and several accumulators, in DSP to generate test patterns. The proposed test pattern generator can generate two test patterns per cycle by using two multiplication processes and an accumulation process. One multiplier has a seed value while another multiplier performs a recursive multiplication. The accumulator performs the addition of two products in order to generate pseudo random test patterns. Consequently, either the two blocks can be tested simultaneously or a block can be tested by using various test-pattern combinations. The results on ISCAS (international symposium, on circuits and systems) benchmark circuits show that the new method can generate test patterns efficiently without LFSRs (linear feedback shift registers).
|Number of pages||8|
|Journal||Journal of the Korean Physical Society|
|Publication status||Published - 2002 Dec 1|
All Science Journal Classification (ASJC) codes
- Physics and Astronomy(all)