Test scheduling of NoC-based SoCs using multiple test clocks

Jin Ho Ahn, Sungho Kang

Research output: Contribution to journalArticle

21 Citations (Scopus)

Abstract

Network-on-chip (NoC) is an emerging design paradigm intended to cope with future systems-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC-based SoCs. Among the existing test issues for NoC-based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC-based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC-based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC'02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC-based SoCs.

Original languageEnglish
Pages (from-to)475-485
Number of pages11
JournalETRI Journal
Volume28
Issue number4
DOIs
Publication statusPublished - 2006 Jan 1

Fingerprint

Clocks
Scheduling
Scheduling algorithms
Testing
Network-on-chip
System-on-chip
Scalability
Energy dissipation
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Computer Science(all)
  • Electrical and Electronic Engineering

Cite this

Ahn, Jin Ho ; Kang, Sungho. / Test scheduling of NoC-based SoCs using multiple test clocks. In: ETRI Journal. 2006 ; Vol. 28, No. 4. pp. 475-485.
@article{b811c0f3957d4031b0756b6acd2a9148,
title = "Test scheduling of NoC-based SoCs using multiple test clocks",
abstract = "Network-on-chip (NoC) is an emerging design paradigm intended to cope with future systems-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC-based SoCs. Among the existing test issues for NoC-based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC-based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC-based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC'02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55{\%}, and 20{\%} on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC-based SoCs.",
author = "Ahn, {Jin Ho} and Sungho Kang",
year = "2006",
month = "1",
day = "1",
doi = "10.4218/etrij.06.0105.0254",
language = "English",
volume = "28",
pages = "475--485",
journal = "ETRI Journal",
issn = "1225-6463",
publisher = "ETRI",
number = "4",

}

Test scheduling of NoC-based SoCs using multiple test clocks. / Ahn, Jin Ho; Kang, Sungho.

In: ETRI Journal, Vol. 28, No. 4, 01.01.2006, p. 475-485.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Test scheduling of NoC-based SoCs using multiple test clocks

AU - Ahn, Jin Ho

AU - Kang, Sungho

PY - 2006/1/1

Y1 - 2006/1/1

N2 - Network-on-chip (NoC) is an emerging design paradigm intended to cope with future systems-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC-based SoCs. Among the existing test issues for NoC-based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC-based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC-based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC'02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC-based SoCs.

AB - Network-on-chip (NoC) is an emerging design paradigm intended to cope with future systems-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC-based SoCs. Among the existing test issues for NoC-based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC-based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC-based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC'02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC-based SoCs.

UR - http://www.scopus.com/inward/record.url?scp=33747187209&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33747187209&partnerID=8YFLogxK

U2 - 10.4218/etrij.06.0105.0254

DO - 10.4218/etrij.06.0105.0254

M3 - Article

AN - SCOPUS:33747187209

VL - 28

SP - 475

EP - 485

JO - ETRI Journal

JF - ETRI Journal

SN - 1225-6463

IS - 4

ER -