Test scheduling using Ant Colony Optimization for 3D integrated circuits

Inhyuk Choi, Taewoo Han, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Cost of test scheduling for the 3D integrated circuits (IC) test is increased compared to the 2D IC due to the constraint factors such as the width of Test Access Mechanism (TAM), the number of Through Silicon Via (TSVs), thermal constraint, and test pin count constraint. In this paper, a low cost test scheduling mechanism using Ant Colony Algorithm (ACO) for the 3D IC is proposed. The experimental results using simulation demonstrate that the proposed algorithm has an effective solution for the 3D IC test scheduling.

Original languageEnglish
Title of host publicationISOCC 2013 - 2013 International SoC Design Conference
PublisherIEEE Computer Society
Pages15-16
Number of pages2
ISBN (Print)9781479911417
DOIs
Publication statusPublished - 2013 Jan 1
Event2013 International SoC Design Conference, ISOCC 2013 - Busan, Korea, Republic of
Duration: 2013 Nov 172013 Nov 19

Publication series

NameISOCC 2013 - 2013 International SoC Design Conference

Other

Other2013 International SoC Design Conference, ISOCC 2013
CountryKorea, Republic of
CityBusan
Period13/11/1713/11/19

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Choi, I., Han, T., & Kang, S. (2013). Test scheduling using Ant Colony Optimization for 3D integrated circuits. In ISOCC 2013 - 2013 International SoC Design Conference (pp. 15-16). [6863973] (ISOCC 2013 - 2013 International SoC Design Conference). IEEE Computer Society. https://doi.org/10.1109/ISOCC.2013.6863973