Test scheduling using Ant Colony Optimization for 3D integrated circuits

Inhyuk Choi, Taewoo Han, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Cost of test scheduling for the 3D integrated circuits (IC) test is increased compared to the 2D IC due to the constraint factors such as the width of Test Access Mechanism (TAM), the number of Through Silicon Via (TSVs), thermal constraint, and test pin count constraint. In this paper, a low cost test scheduling mechanism using Ant Colony Algorithm (ACO) for the 3D IC is proposed. The experimental results using simulation demonstrate that the proposed algorithm has an effective solution for the 3D IC test scheduling.

Original languageEnglish
Title of host publicationISOCC 2013 - 2013 International SoC Design Conference
PublisherIEEE Computer Society
Pages15-16
Number of pages2
ISBN (Print)9781479911417
DOIs
Publication statusPublished - 2013 Jan 1
Event2013 International SoC Design Conference, ISOCC 2013 - Busan, Korea, Republic of
Duration: 2013 Nov 172013 Nov 19

Publication series

NameISOCC 2013 - 2013 International SoC Design Conference

Other

Other2013 International SoC Design Conference, ISOCC 2013
CountryKorea, Republic of
CityBusan
Period13/11/1713/11/19

Fingerprint

Ant colony optimization
Scheduling
Integrated circuits
Costs
Silicon
Three dimensional integrated circuits

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Choi, I., Han, T., & Kang, S. (2013). Test scheduling using Ant Colony Optimization for 3D integrated circuits. In ISOCC 2013 - 2013 International SoC Design Conference (pp. 15-16). [6863973] (ISOCC 2013 - 2013 International SoC Design Conference). IEEE Computer Society. https://doi.org/10.1109/ISOCC.2013.6863973
Choi, Inhyuk ; Han, Taewoo ; Kang, Sungho. / Test scheduling using Ant Colony Optimization for 3D integrated circuits. ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society, 2013. pp. 15-16 (ISOCC 2013 - 2013 International SoC Design Conference).
@inproceedings{876c561561ca41de98360d97483c4057,
title = "Test scheduling using Ant Colony Optimization for 3D integrated circuits",
abstract = "Cost of test scheduling for the 3D integrated circuits (IC) test is increased compared to the 2D IC due to the constraint factors such as the width of Test Access Mechanism (TAM), the number of Through Silicon Via (TSVs), thermal constraint, and test pin count constraint. In this paper, a low cost test scheduling mechanism using Ant Colony Algorithm (ACO) for the 3D IC is proposed. The experimental results using simulation demonstrate that the proposed algorithm has an effective solution for the 3D IC test scheduling.",
author = "Inhyuk Choi and Taewoo Han and Sungho Kang",
year = "2013",
month = "1",
day = "1",
doi = "10.1109/ISOCC.2013.6863973",
language = "English",
isbn = "9781479911417",
series = "ISOCC 2013 - 2013 International SoC Design Conference",
publisher = "IEEE Computer Society",
pages = "15--16",
booktitle = "ISOCC 2013 - 2013 International SoC Design Conference",
address = "United States",

}

Choi, I, Han, T & Kang, S 2013, Test scheduling using Ant Colony Optimization for 3D integrated circuits. in ISOCC 2013 - 2013 International SoC Design Conference., 6863973, ISOCC 2013 - 2013 International SoC Design Conference, IEEE Computer Society, pp. 15-16, 2013 International SoC Design Conference, ISOCC 2013, Busan, Korea, Republic of, 13/11/17. https://doi.org/10.1109/ISOCC.2013.6863973

Test scheduling using Ant Colony Optimization for 3D integrated circuits. / Choi, Inhyuk; Han, Taewoo; Kang, Sungho.

ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society, 2013. p. 15-16 6863973 (ISOCC 2013 - 2013 International SoC Design Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Test scheduling using Ant Colony Optimization for 3D integrated circuits

AU - Choi, Inhyuk

AU - Han, Taewoo

AU - Kang, Sungho

PY - 2013/1/1

Y1 - 2013/1/1

N2 - Cost of test scheduling for the 3D integrated circuits (IC) test is increased compared to the 2D IC due to the constraint factors such as the width of Test Access Mechanism (TAM), the number of Through Silicon Via (TSVs), thermal constraint, and test pin count constraint. In this paper, a low cost test scheduling mechanism using Ant Colony Algorithm (ACO) for the 3D IC is proposed. The experimental results using simulation demonstrate that the proposed algorithm has an effective solution for the 3D IC test scheduling.

AB - Cost of test scheduling for the 3D integrated circuits (IC) test is increased compared to the 2D IC due to the constraint factors such as the width of Test Access Mechanism (TAM), the number of Through Silicon Via (TSVs), thermal constraint, and test pin count constraint. In this paper, a low cost test scheduling mechanism using Ant Colony Algorithm (ACO) for the 3D IC is proposed. The experimental results using simulation demonstrate that the proposed algorithm has an effective solution for the 3D IC test scheduling.

UR - http://www.scopus.com/inward/record.url?scp=84906912232&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84906912232&partnerID=8YFLogxK

U2 - 10.1109/ISOCC.2013.6863973

DO - 10.1109/ISOCC.2013.6863973

M3 - Conference contribution

SN - 9781479911417

T3 - ISOCC 2013 - 2013 International SoC Design Conference

SP - 15

EP - 16

BT - ISOCC 2013 - 2013 International SoC Design Conference

PB - IEEE Computer Society

ER -

Choi I, Han T, Kang S. Test scheduling using Ant Colony Optimization for 3D integrated circuits. In ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society. 2013. p. 15-16. 6863973. (ISOCC 2013 - 2013 International SoC Design Conference). https://doi.org/10.1109/ISOCC.2013.6863973