Testability strategy and DFT methodology of CalmRISC32

Hong Sik Kim, Il Seok Seo, Sungho Kang, Gunhee Han

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper describes the test strategy and the DFT (Design for Testability) methodology of CalmRISC32. CalmRISC32 is a 32 bit microcontrol unit, which consists of a 32 bit IU core, an FPU and a Cache Unit. The embedded memory arrays are tested by memory BIST (Built-in Self Test) and the logic blocks are tested by functional test methodology at the instruction level. To increase the test efficiency, a new scan chain methodology using a module called a TSU (Test Scan Unit) is developed.

Original languageEnglish
Title of host publicationProceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages295-298
Number of pages4
ISBN (Electronic)0780364708, 9780780364707
DOIs
Publication statusPublished - 2000 Jan 1
Event2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000 - Cheju, Korea, Republic of
Duration: 2000 Aug 282000 Aug 30

Publication series

NameProceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000

Other

Other2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000
CountryKorea, Republic of
CityCheju
Period00/8/2800/8/30

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Testability strategy and DFT methodology of CalmRISC32'. Together they form a unique fingerprint.

  • Cite this

    Kim, H. S., Seo, I. S., Kang, S., & Han, G. (2000). Testability strategy and DFT methodology of CalmRISC32. In Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000 (pp. 295-298). [896966] (Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APASIC.2000.896966