The challenges in introducing PMOS dual channel in CMOS processing

H. R. Harris; Prashant Majhi; Paul Kirsch; Prasanna Sivasubramani; Jung Woo Oh; S. C. Song

doi:10.1149/1.3118948

The challenges in introducing PMOS dual channel in CMOS processing

H. R. Harris, Prashant Majhi, Paul Kirsch, Prasanna Sivasubramani, Jung Woo Oh, S. C. Song

School of Integrated Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The benefit of a SiGe channel in the adjustment of the threshold voltage in PMOS devices is outlined. However, difficulties in the implementation make the full CMOS integration challenging. We examine these difficulties of implementation and the complexities of the processes. The issues are divided into two categories to better understand the complexity: active area related and complementary process related. In particular, the process issues associated with epitaxy, gate etch, silicide and lithography are particularly examined. It is concluded that the issues can be overcome with excellent transistor results.

Original language	English
Title of host publication	ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 5
Subtitle of host publication	New Materials, Processes, and Equipment
Publisher	Electrochemical Society Inc.
Pages	223-231
Number of pages	9
Edition	1
ISBN (Electronic)	9781607680598
ISBN (Print)	9781566777094
DOIs	https://doi.org/10.1149/1.3118948
Publication status	Published - 2009
Event	International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment - 215th ECS Meeting - San Francisco, CA, United States Duration: 2009 May 24 → 2009 May 29

Publication series

Name	ECS Transactions
Number	1
Volume	19
ISSN (Print)	1938-5862
ISSN (Electronic)	1938-6737

Other

Other	International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment - 215th ECS Meeting
Country/Territory	United States
City	San Francisco, CA
Period	09/5/24 → 09/5/29

All Science Journal Classification (ASJC) codes

Engineering(all)

Access to Document

10.1149/1.3118948

Cite this

Harris, H. R., Majhi, P., Kirsch, P., Sivasubramani, P., Oh, J. W., & Song, S. C. (2009). The challenges in introducing PMOS dual channel in CMOS processing. In ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 5: New Materials, Processes, and Equipment (1 ed., pp. 223-231). (ECS Transactions; Vol. 19, No. 1). Electrochemical Society Inc.. https://doi.org/10.1149/1.3118948

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abstract = "The benefit of a SiGe channel in the adjustment of the threshold voltage in PMOS devices is outlined. However, difficulties in the implementation make the full CMOS integration challenging. We examine these difficulties of implementation and the complexities of the processes. The issues are divided into two categories to better understand the complexity: active area related and complementary process related. In particular, the process issues associated with epitaxy, gate etch, silicide and lithography are particularly examined. It is concluded that the issues can be overcome with excellent transistor results.",

author = "Harris, {H. R.} and Prashant Majhi and Paul Kirsch and Prasanna Sivasubramani and Oh, {Jung Woo} and Song, {S. C.}",

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series = "ECS Transactions",

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booktitle = "ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 5",

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note = "International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment - 215th ECS Meeting ; Conference date: 24-05-2009 Through 29-05-2009",

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Harris, HR, Majhi, P, Kirsch, P, Sivasubramani, P, Oh, JW & Song, SC 2009, The challenges in introducing PMOS dual channel in CMOS processing. in ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 5: New Materials, Processes, and Equipment. 1 edn, ECS Transactions, no. 1, vol. 19, Electrochemical Society Inc., pp. 223-231, International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment - 215th ECS Meeting, San Francisco, CA, United States, 09/5/24. https://doi.org/10.1149/1.3118948

The challenges in introducing PMOS dual channel in CMOS processing. / Harris, H. R.; Majhi, Prashant; Kirsch, Paul et al.

ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 5: New Materials, Processes, and Equipment. 1. ed. Electrochemical Society Inc., 2009. p. 223-231 (ECS Transactions; Vol. 19, No. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Harris HR, Majhi P, Kirsch P, Sivasubramani P, Oh JW, Song SC. The challenges in introducing PMOS dual channel in CMOS processing. In ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 5: New Materials, Processes, and Equipment. 1 ed. Electrochemical Society Inc. 2009. p. 223-231. (ECS Transactions; 1). doi: 10.1149/1.3118948

The challenges in introducing PMOS dual channel in CMOS processing

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