The challenges in introducing PMOS dual channel in CMOS processing

H. R. Harris, Prashant Majhi, Paul Kirsch, Prasanna Sivasubramani, Jung Woo Oh, S. C. Song

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The benefit of a SiGe channel in the adjustment of the threshold voltage in PMOS devices is outlined. However, difficulties in the implementation make the full CMOS integration challenging. We examine these difficulties of implementation and the complexities of the processes. The issues are divided into two categories to better understand the complexity: active area related and complementary process related. In particular, the process issues associated with epitaxy, gate etch, silicide and lithography are particularly examined. It is concluded that the issues can be overcome with excellent transistor results.

Original languageEnglish
Title of host publicationECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 5
Subtitle of host publicationNew Materials, Processes, and Equipment
Pages223-231
Number of pages9
Edition1
DOIs
Publication statusPublished - 2009 Dec 1
EventInternational Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment - 215th ECS Meeting - San Francisco, CA, United States
Duration: 2009 May 242009 May 29

Publication series

NameECS Transactions
Number1
Volume19
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

OtherInternational Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment - 215th ECS Meeting
CountryUnited States
CitySan Francisco, CA
Period09/5/2409/5/29

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Harris, H. R., Majhi, P., Kirsch, P., Sivasubramani, P., Oh, J. W., & Song, S. C. (2009). The challenges in introducing PMOS dual channel in CMOS processing. In ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 5: New Materials, Processes, and Equipment (1 ed., pp. 223-231). (ECS Transactions; Vol. 19, No. 1). https://doi.org/10.1149/1.3118948