Abstract
The benefit of a SiGe channel in the adjustment of the threshold voltage in PMOS devices is outlined. However, difficulties in the implementation make the full CMOS integration challenging. We examine these difficulties of implementation and the complexities of the processes. The issues are divided into two categories to better understand the complexity: active area related and complementary process related. In particular, the process issues associated with epitaxy, gate etch, silicide and lithography are particularly examined. It is concluded that the issues can be overcome with excellent transistor results.
| Original language | English |
|---|---|
| Title of host publication | ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 5 |
| Subtitle of host publication | New Materials, Processes, and Equipment |
| Pages | 223-231 |
| Number of pages | 9 |
| Edition | 1 |
| DOIs | |
| Publication status | Published - 2009 Dec 1 |
| Event | International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment - 215th ECS Meeting - San Francisco, CA, United States Duration: 2009 May 24 → 2009 May 29 |
Publication series
| Name | ECS Transactions |
|---|---|
| Number | 1 |
| Volume | 19 |
| ISSN (Print) | 1938-5862 |
| ISSN (Electronic) | 1938-6737 |
Other
| Other | International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment - 215th ECS Meeting |
|---|---|
| Country | United States |
| City | San Francisco, CA |
| Period | 09/5/24 → 09/5/29 |
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All Science Journal Classification (ASJC) codes
- Engineering(all)
Cite this
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The challenges in introducing PMOS dual channel in CMOS processing. / Harris, H. R.; Majhi, Prashant; Kirsch, Paul; Sivasubramani, Prasanna; Oh, Jungwoo; Song, S. C.
ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 5: New Materials, Processes, and Equipment. 1. ed. 2009. p. 223-231 (ECS Transactions; Vol. 19, No. 1).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - The challenges in introducing PMOS dual channel in CMOS processing
AU - Harris, H. R.
AU - Majhi, Prashant
AU - Kirsch, Paul
AU - Sivasubramani, Prasanna
AU - Oh, Jungwoo
AU - Song, S. C.
PY - 2009/12/1
Y1 - 2009/12/1
N2 - The benefit of a SiGe channel in the adjustment of the threshold voltage in PMOS devices is outlined. However, difficulties in the implementation make the full CMOS integration challenging. We examine these difficulties of implementation and the complexities of the processes. The issues are divided into two categories to better understand the complexity: active area related and complementary process related. In particular, the process issues associated with epitaxy, gate etch, silicide and lithography are particularly examined. It is concluded that the issues can be overcome with excellent transistor results.
AB - The benefit of a SiGe channel in the adjustment of the threshold voltage in PMOS devices is outlined. However, difficulties in the implementation make the full CMOS integration challenging. We examine these difficulties of implementation and the complexities of the processes. The issues are divided into two categories to better understand the complexity: active area related and complementary process related. In particular, the process issues associated with epitaxy, gate etch, silicide and lithography are particularly examined. It is concluded that the issues can be overcome with excellent transistor results.
UR - http://www.scopus.com/inward/record.url?scp=74949119442&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=74949119442&partnerID=8YFLogxK
U2 - 10.1149/1.3118948
DO - 10.1149/1.3118948
M3 - Conference contribution
SN - 9781566777094
T3 - ECS Transactions
SP - 223
EP - 231
BT - ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 5
ER -