Pentacene-based thin film transistors with ultrathin (6 nm) (HfO 2)x(SiO2)1-x gate dielectric layers (x=0.25 and 0.75) were fabricated for low-voltage operation. The devices with ultrathin (HfO2)x(SiO2)1-x as the gate dielectric layer were operated at a gate voltage lower than -4.0 eV. However, the threshold voltage and drain current have different values depending on the composition of the (Hf O2)x (Si O2)1-x gate dielectric layer. The device with (HfO2)0.75(SiO2)0.25 gate dielectrics, having larger capacitance, shows a higher drain current than that with (HfO2)0.75(SiO2)0.25 gate dielectrics. On the other hand, the device with (HfO2) 0.75(SiO2)0.25 gate dielectrics, which has a larger work function, shows a lower threshold voltage. The in situ ultraviolet photoelectron spectroscopy shows that this is caused by the difference in electronic structures and by changes in band alignment of the interface between the pentacene and dielectric layers.
Bibliographical noteFunding Information:
This work is supported by the BK21 project of the Korea Research Foundation (KRF) and the National Program for Tera-level Nanodevices of the Ministry of Science and Technology as one of the 21 Century Frontier Programs.
All Science Journal Classification (ASJC) codes
- Physics and Astronomy (miscellaneous)