TY - GEN
T1 - The design of the perspective texture mapping for 3D computer graphics in rasterizer merged frame buffer technology
AU - Lee, Seung Gi
AU - Park, Woo Chan
AU - Lee, Won Jong
AU - Jung, Woo Nam
AU - Han, Tack Don
N1 - Publisher Copyright:
© 2000 IEEE.
Copyright:
Copyright 2016 Elsevier B.V., All rights reserved.
PY - 2000
Y1 - 2000
N2 - Recently, more advanced image quality and many techniques are needed in 3D computer graphics. Especially texture mapping support is the major issue in the design of high performance 3D graphics system. In this paper, a high-performance 3D graphics hardware is designed for texture mapping. The proposed system is composed of a single-chip rasterizer and frame buffer using a processor-memory integration method, which is adapted for processing high-performance 3D graphics. Also, the texture mapping unit is designed using the processor-memory integration technology to provide sufficient bandwidth. Therefore, the tremendous memory bandwidth and the long latency required for texture mapping can be reduced by this approach.
AB - Recently, more advanced image quality and many techniques are needed in 3D computer graphics. Especially texture mapping support is the major issue in the design of high performance 3D graphics system. In this paper, a high-performance 3D graphics hardware is designed for texture mapping. The proposed system is composed of a single-chip rasterizer and frame buffer using a processor-memory integration method, which is adapted for processing high-performance 3D graphics. Also, the texture mapping unit is designed using the processor-memory integration technology to provide sufficient bandwidth. Therefore, the tremendous memory bandwidth and the long latency required for texture mapping can be reduced by this approach.
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U2 - 10.1109/APASIC.2000.896948
DO - 10.1109/APASIC.2000.896948
M3 - Conference contribution
AN - SCOPUS:85010228379
T3 - Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000
SP - 219
EP - 222
BT - Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000
Y2 - 28 August 2000 through 30 August 2000
ER -