The design of the perspective texture mapping for 3D computer graphics in rasterizer merged frame buffer technology

Seung Gi Lee; Woo Chan Park; Won Jong Lee; Woo Nam Jung; Tack Don Han

doi:10.1109/APASIC.2000.896948

The design of the perspective texture mapping for 3D computer graphics in rasterizer merged frame buffer technology

Seung Gi Lee, Woo Chan Park, Won Jong Lee, Woo Nam Jung, Tack Don Han

Department of Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Recently, more advanced image quality and many techniques are needed in 3D computer graphics. Especially texture mapping support is the major issue in the design of high performance 3D graphics system. In this paper, a high-performance 3D graphics hardware is designed for texture mapping. The proposed system is composed of a single-chip rasterizer and frame buffer using a processor-memory integration method, which is adapted for processing high-performance 3D graphics. Also, the texture mapping unit is designed using the processor-memory integration technology to provide sufficient bandwidth. Therefore, the tremendous memory bandwidth and the long latency required for texture mapping can be reduced by this approach.

Original language	English
Title of host publication	Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	219-222
Number of pages	4
ISBN (Electronic)	0780364708, 9780780364707
DOIs	https://doi.org/10.1109/APASIC.2000.896948
Publication status	Published - 2000 Jan 1
Event	2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000 - Cheju, Korea, Republic of Duration: 2000 Aug 28 → 2000 Aug 30

Publication series

Name	Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000

Other

Other	2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000
Country	Korea, Republic of
City	Cheju
Period	00/8/28 → 00/8/30

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/APASIC.2000.896948

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Lee, S. G., Park, W. C., Lee, W. J., Jung, W. N., & Han, T. D. (2000). The design of the perspective texture mapping for 3D computer graphics in rasterizer merged frame buffer technology. In Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000 (pp. 219-222). [896948] (Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APASIC.2000.896948

Lee, Seung Gi ; Park, Woo Chan ; Lee, Won Jong ; Jung, Woo Nam ; Han, Tack Don. / The design of the perspective texture mapping for 3D computer graphics in rasterizer merged frame buffer technology. Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000. Institute of Electrical and Electronics Engineers Inc., 2000. pp. 219-222 (Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000).

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title = "The design of the perspective texture mapping for 3D computer graphics in rasterizer merged frame buffer technology",

abstract = "Recently, more advanced image quality and many techniques are needed in 3D computer graphics. Especially texture mapping support is the major issue in the design of high performance 3D graphics system. In this paper, a high-performance 3D graphics hardware is designed for texture mapping. The proposed system is composed of a single-chip rasterizer and frame buffer using a processor-memory integration method, which is adapted for processing high-performance 3D graphics. Also, the texture mapping unit is designed using the processor-memory integration technology to provide sufficient bandwidth. Therefore, the tremendous memory bandwidth and the long latency required for texture mapping can be reduced by this approach.",

author = "Lee, {Seung Gi} and Park, {Woo Chan} and Lee, {Won Jong} and Jung, {Woo Nam} and Han, {Tack Don}",

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booktitle = "Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000",

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note = "2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000 ; Conference date: 28-08-2000 Through 30-08-2000",

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Lee, SG, Park, WC, Lee, WJ, Jung, WN & Han, TD 2000, The design of the perspective texture mapping for 3D computer graphics in rasterizer merged frame buffer technology. in Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000., 896948, Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000, Institute of Electrical and Electronics Engineers Inc., pp. 219-222, 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000, Cheju, Korea, Republic of, 00/8/28. https://doi.org/10.1109/APASIC.2000.896948

The design of the perspective texture mapping for 3D computer graphics in rasterizer merged frame buffer technology. / Lee, Seung Gi; Park, Woo Chan; Lee, Won Jong; Jung, Woo Nam; Han, Tack Don.

Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000. Institute of Electrical and Electronics Engineers Inc., 2000. p. 219-222 896948 (Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - Recently, more advanced image quality and many techniques are needed in 3D computer graphics. Especially texture mapping support is the major issue in the design of high performance 3D graphics system. In this paper, a high-performance 3D graphics hardware is designed for texture mapping. The proposed system is composed of a single-chip rasterizer and frame buffer using a processor-memory integration method, which is adapted for processing high-performance 3D graphics. Also, the texture mapping unit is designed using the processor-memory integration technology to provide sufficient bandwidth. Therefore, the tremendous memory bandwidth and the long latency required for texture mapping can be reduced by this approach.

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Lee SG, Park WC, Lee WJ, Jung WN, Han TD. The design of the perspective texture mapping for 3D computer graphics in rasterizer merged frame buffer technology. In Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000. Institute of Electrical and Electronics Engineers Inc. 2000. p. 219-222. 896948. (Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs, AP-ASIC 2000). https://doi.org/10.1109/APASIC.2000.896948