Abstract
We report on new observations of hot carrier (HC) degradation in strained Si/Sil-xGex(x =0.2 to 0.5) p-MOSFETs. By using low voltage current-voltage measurement coupled with carrier separation, we are able, for the first time, to easily distinguish the energy distribution of the interface traps. High-K dielectrics on SiGe p-channel show higher interface traps generation located close to conduction band under channel hot carrier stressing and uniform interface trap under drain avalanche hot carrier stressing, both of which can be mitigated by increasing Ge% in the Si/SiGe channel. Detailed study on Si capping layer (=≤ 20Å) shows good immunity against Drain Avalanche Hot Carrier but is degraded under Channel Hot Carrier stressing. The results suggest that higher Ge% and thinner Si cap is preferably for hot carrier reliability for low voltage application with 10yrs lifetime at operating voltage of -0.85 V.
| Original language | English |
|---|---|
| Title of host publication | 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT |
| Pages | 56-57 |
| Number of pages | 2 |
| DOIs | |
| Publication status | Published - 2008 Sep 23 |
| Event | 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT - Honolulu, HI, United States Duration: 2008 Jun 17 → 2008 Jun 19 |
Publication series
| Name | Digest of Technical Papers - Symposium on VLSI Technology |
|---|---|
| ISSN (Print) | 0743-1562 |
Other
| Other | 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT |
|---|---|
| Country | United States |
| City | Honolulu, HI |
| Period | 08/6/17 → 08/6/19 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
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The effects of Ge composition and Si cap thickness on hot carrier reliability of Si/Sil-xGex/Si p-MOSFETs with high-K/metal gate. / Loh, W. Y.; Majhi, P.; Lee, S. H.; Oh, J. W.; Sassman, B.; Young, C.; Bersuker, G.; Cho, B. J.; Park, C. S.; Kang, C. Y.; Kirsch, P.; Lee, B. H.; Harris, H. R.; Tseng, H. H.; Jammy, R.
2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT. 2008. p. 56-57 4588562 (Digest of Technical Papers - Symposium on VLSI Technology).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - The effects of Ge composition and Si cap thickness on hot carrier reliability of Si/Sil-xGex/Si p-MOSFETs with high-K/metal gate
AU - Loh, W. Y.
AU - Majhi, P.
AU - Lee, S. H.
AU - Oh, J. W.
AU - Sassman, B.
AU - Young, C.
AU - Bersuker, G.
AU - Cho, B. J.
AU - Park, C. S.
AU - Kang, C. Y.
AU - Kirsch, P.
AU - Lee, B. H.
AU - Harris, H. R.
AU - Tseng, H. H.
AU - Jammy, R.
PY - 2008/9/23
Y1 - 2008/9/23
N2 - We report on new observations of hot carrier (HC) degradation in strained Si/Sil-xGex(x =0.2 to 0.5) p-MOSFETs. By using low voltage current-voltage measurement coupled with carrier separation, we are able, for the first time, to easily distinguish the energy distribution of the interface traps. High-K dielectrics on SiGe p-channel show higher interface traps generation located close to conduction band under channel hot carrier stressing and uniform interface trap under drain avalanche hot carrier stressing, both of which can be mitigated by increasing Ge% in the Si/SiGe channel. Detailed study on Si capping layer (=≤ 20Å) shows good immunity against Drain Avalanche Hot Carrier but is degraded under Channel Hot Carrier stressing. The results suggest that higher Ge% and thinner Si cap is preferably for hot carrier reliability for low voltage application with 10yrs lifetime at operating voltage of -0.85 V.
AB - We report on new observations of hot carrier (HC) degradation in strained Si/Sil-xGex(x =0.2 to 0.5) p-MOSFETs. By using low voltage current-voltage measurement coupled with carrier separation, we are able, for the first time, to easily distinguish the energy distribution of the interface traps. High-K dielectrics on SiGe p-channel show higher interface traps generation located close to conduction band under channel hot carrier stressing and uniform interface trap under drain avalanche hot carrier stressing, both of which can be mitigated by increasing Ge% in the Si/SiGe channel. Detailed study on Si capping layer (=≤ 20Å) shows good immunity against Drain Avalanche Hot Carrier but is degraded under Channel Hot Carrier stressing. The results suggest that higher Ge% and thinner Si cap is preferably for hot carrier reliability for low voltage application with 10yrs lifetime at operating voltage of -0.85 V.
UR - http://www.scopus.com/inward/record.url?scp=51949102511&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=51949102511&partnerID=8YFLogxK
U2 - 10.1109/VLSIT.2008.4588562
DO - 10.1109/VLSIT.2008.4588562
M3 - Conference contribution
AN - SCOPUS:51949102511
SN - 9781424418053
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - 56
EP - 57
BT - 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT
ER -