The effects of Ge composition and Si cap thickness on hot carrier reliability of Si/Sil-xGex/Si p-MOSFETs with high-K/metal gate

W. Y. Loh, P. Majhi, S. H. Lee, J. W. Oh, B. Sassman, C. Young, G. Bersuker, B. J. Cho, C. S. Park, C. Y. Kang, P. Kirsch, B. H. Lee, H. R. Harris, H. H. Tseng, R. Jammy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

We report on new observations of hot carrier (HC) degradation in strained Si/Sil-xGex(x =0.2 to 0.5) p-MOSFETs. By using low voltage current-voltage measurement coupled with carrier separation, we are able, for the first time, to easily distinguish the energy distribution of the interface traps. High-K dielectrics on SiGe p-channel show higher interface traps generation located close to conduction band under channel hot carrier stressing and uniform interface trap under drain avalanche hot carrier stressing, both of which can be mitigated by increasing Ge% in the Si/SiGe channel. Detailed study on Si capping layer (=≤ 20Å) shows good immunity against Drain Avalanche Hot Carrier but is degraded under Channel Hot Carrier stressing. The results suggest that higher Ge% and thinner Si cap is preferably for hot carrier reliability for low voltage application with 10yrs lifetime at operating voltage of -0.85 V.

Original languageEnglish
Title of host publication2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT
Pages56-57
Number of pages2
DOIs
Publication statusPublished - 2008
Event2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT - Honolulu, HI, United States
Duration: 2008 Jun 172008 Jun 19

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT
CountryUnited States
CityHonolulu, HI
Period08/6/1708/6/19

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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