The electrical properties of low temperature polycrystalline si thin film transistor prepared by nickel-ALD process

Seung Min Lee, Choong Hee Lee, Tae Hoon Jeong, Hyun Jae Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

We have fabricated low temperature polycrystalline Si thin film transistors (LTPS TFTs) for flat panel displays. In this work, metal induced crystallization (MIC) using atomic layer deposition (ALD) was employed to obtain poly-Si as an active layer in LTPS TFTs. The small amounts of nickel atoms by ALD were deposited on amorphous Si to minimize the metal contaminations. The poly-Si thin films have large and uniform grains with average size of 27 um by self-limited reaction process of ALD. The n-type LTPS TFT exhibits a high field effect mobility of about 76 cm2/Vs, a sub-threshold slope of 0.09 V, a threshold voltage of 4.79 V, and an on-off ratio of 4.9 x 106.

Original languageEnglish
Title of host publicationECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4
Subtitle of host publicationNew Materials, Processes, and Equipment
Pages367-374
Number of pages8
Edition1
DOIs
Publication statusPublished - 2008 Nov 13
EventAdvanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment, 4 - Phoenix, AZ, United States
Duration: 2008 May 182008 May 22

Publication series

NameECS Transactions
Number1
Volume13
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

OtherAdvanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment, 4
CountryUnited States
CityPhoenix, AZ
Period08/5/1808/5/22

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All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Lee, S. M., Lee, C. H., Jeong, T. H., & Kim, H. J. (2008). The electrical properties of low temperature polycrystalline si thin film transistor prepared by nickel-ALD process. In ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4: New Materials, Processes, and Equipment (1 ed., pp. 367-374). (ECS Transactions; Vol. 13, No. 1). https://doi.org/10.1149/1.2911519