The excellent scalability of the RCAT(Recess-Channel-Array-Transistor) technology for sub-70nm DRAM feature size and beyond

J. Y. Kim, D. S. Woo, H. J. Oh, H. J. Kim, S. E. Kim, B. J. Park, J. M. Kwon, M. S. Shim, G. W. Ha, J. W. Song, N. J. Kang, J. M. Park, H. K. Hwang, S. S. Song, Y. S. Hwang, D. I. Kim, D. H. Kim, M. Huh, D. H. Han, C. S. LeeS. J. Park, Y. R. Kim, H. J. Kim, Y. S. Lee, M. Y. Jung, Y. I. Kim, B. H. Lee, M. H. Cho, W. T. Choi, H. S. Kim, G. Y. Jin, Y. J. Park, Kinam Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

The technology innovation for extending the RCAT structure to the sub-70nm DRAM is presented The new technology overcomes the problems induced by shrinkage of the RCAT structure and meets the requirements for the next generation DRAMs, such as high speed and low power performance. The technology roadmap down to the 50nm DRAM feature size of the RCAT development is presented.

Original languageEnglish
Title of host publication2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers
Pages33-34
Number of pages2
Publication statusPublished - 2005
Event2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH - Hsinchu, Taiwan, Province of China
Duration: 2005 Apr 252005 Apr 27

Publication series

Name2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers

Other

Other2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH
CountryTaiwan, Province of China
CityHsinchu
Period05/4/2505/4/27

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Kim, J. Y., Woo, D. S., Oh, H. J., Kim, H. J., Kim, S. E., Park, B. J., Kwon, J. M., Shim, M. S., Ha, G. W., Song, J. W., Kang, N. J., Park, J. M., Hwang, H. K., Song, S. S., Hwang, Y. S., Kim, D. I., Kim, D. H., Huh, M., Han, D. H., ... Kim, K. (2005). The excellent scalability of the RCAT(Recess-Channel-Array-Transistor) technology for sub-70nm DRAM feature size and beyond. In 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers (pp. 33-34). [T23] (2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers).