The fabrication of the p-type ultra low temperature TFT under 200°C

Hyuck Lim, Kyung Bae Park, Huaxlang Yin, Wenxu Xianyu, Jang Yaon Kwon, Xiaoxin Zhang, Hans S. Cho, Jong Man Kim, Do Young Kim, Ji Sim Jung, Takashi Noguchi

Research output: Contribution to conferencePaper

Abstract

We studied the p-channel (p-ch.) poly silicon (Si) thin film transistor (TFT) using ultra low temperature processes below 200°C. By performing the low temperature thermal annealing after obtaining TFT, the device performances, such as the mobility of 64 cm cm2/Vs, and the sub-threshold slope (S.S) of 0.74 Vldec., improved drastically. The p-ch. circuits or complementary MOS (CMOS) design on plastic is expected for future advanced flexible flat panel display (FPD).

Original languageEnglish
Pages1159-1161
Number of pages3
Publication statusPublished - 2005 Dec 1
EventIDW/AD'05 - 12th International Display Workshops in Conjunction with Asia Display 2005 - Takamatsu, Japan
Duration: 2005 Dec 62005 Dec 9

Other

OtherIDW/AD'05 - 12th International Display Workshops in Conjunction with Asia Display 2005
CountryJapan
CityTakamatsu
Period05/12/605/12/9

Fingerprint

Thin film transistors
Flexible displays
Fabrication
Flat panel displays
Annealing
Plastics
Silicon
Temperature
Networks (circuits)
Hot Temperature

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Lim, H., Park, K. B., Yin, H., Xianyu, W., Kwon, J. Y., Zhang, X., ... Noguchi, T. (2005). The fabrication of the p-type ultra low temperature TFT under 200°C. 1159-1161. Paper presented at IDW/AD'05 - 12th International Display Workshops in Conjunction with Asia Display 2005, Takamatsu, Japan.
Lim, Hyuck ; Park, Kyung Bae ; Yin, Huaxlang ; Xianyu, Wenxu ; Kwon, Jang Yaon ; Zhang, Xiaoxin ; Cho, Hans S. ; Kim, Jong Man ; Kim, Do Young ; Jung, Ji Sim ; Noguchi, Takashi. / The fabrication of the p-type ultra low temperature TFT under 200°C. Paper presented at IDW/AD'05 - 12th International Display Workshops in Conjunction with Asia Display 2005, Takamatsu, Japan.3 p.
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abstract = "We studied the p-channel (p-ch.) poly silicon (Si) thin film transistor (TFT) using ultra low temperature processes below 200°C. By performing the low temperature thermal annealing after obtaining TFT, the device performances, such as the mobility of 64 cm cm2/Vs, and the sub-threshold slope (S.S) of 0.74 Vldec., improved drastically. The p-ch. circuits or complementary MOS (CMOS) design on plastic is expected for future advanced flexible flat panel display (FPD).",
author = "Hyuck Lim and Park, {Kyung Bae} and Huaxlang Yin and Wenxu Xianyu and Kwon, {Jang Yaon} and Xiaoxin Zhang and Cho, {Hans S.} and Kim, {Jong Man} and Kim, {Do Young} and Jung, {Ji Sim} and Takashi Noguchi",
year = "2005",
month = "12",
day = "1",
language = "English",
pages = "1159--1161",
note = "IDW/AD'05 - 12th International Display Workshops in Conjunction with Asia Display 2005 ; Conference date: 06-12-2005 Through 09-12-2005",

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Lim, H, Park, KB, Yin, H, Xianyu, W, Kwon, JY, Zhang, X, Cho, HS, Kim, JM, Kim, DY, Jung, JS & Noguchi, T 2005, 'The fabrication of the p-type ultra low temperature TFT under 200°C', Paper presented at IDW/AD'05 - 12th International Display Workshops in Conjunction with Asia Display 2005, Takamatsu, Japan, 05/12/6 - 05/12/9 pp. 1159-1161.

The fabrication of the p-type ultra low temperature TFT under 200°C. / Lim, Hyuck; Park, Kyung Bae; Yin, Huaxlang; Xianyu, Wenxu; Kwon, Jang Yaon; Zhang, Xiaoxin; Cho, Hans S.; Kim, Jong Man; Kim, Do Young; Jung, Ji Sim; Noguchi, Takashi.

2005. 1159-1161 Paper presented at IDW/AD'05 - 12th International Display Workshops in Conjunction with Asia Display 2005, Takamatsu, Japan.

Research output: Contribution to conferencePaper

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T1 - The fabrication of the p-type ultra low temperature TFT under 200°C

AU - Lim, Hyuck

AU - Park, Kyung Bae

AU - Yin, Huaxlang

AU - Xianyu, Wenxu

AU - Kwon, Jang Yaon

AU - Zhang, Xiaoxin

AU - Cho, Hans S.

AU - Kim, Jong Man

AU - Kim, Do Young

AU - Jung, Ji Sim

AU - Noguchi, Takashi

PY - 2005/12/1

Y1 - 2005/12/1

N2 - We studied the p-channel (p-ch.) poly silicon (Si) thin film transistor (TFT) using ultra low temperature processes below 200°C. By performing the low temperature thermal annealing after obtaining TFT, the device performances, such as the mobility of 64 cm cm2/Vs, and the sub-threshold slope (S.S) of 0.74 Vldec., improved drastically. The p-ch. circuits or complementary MOS (CMOS) design on plastic is expected for future advanced flexible flat panel display (FPD).

AB - We studied the p-channel (p-ch.) poly silicon (Si) thin film transistor (TFT) using ultra low temperature processes below 200°C. By performing the low temperature thermal annealing after obtaining TFT, the device performances, such as the mobility of 64 cm cm2/Vs, and the sub-threshold slope (S.S) of 0.74 Vldec., improved drastically. The p-ch. circuits or complementary MOS (CMOS) design on plastic is expected for future advanced flexible flat panel display (FPD).

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Lim H, Park KB, Yin H, Xianyu W, Kwon JY, Zhang X et al. The fabrication of the p-type ultra low temperature TFT under 200°C. 2005. Paper presented at IDW/AD'05 - 12th International Display Workshops in Conjunction with Asia Display 2005, Takamatsu, Japan.