We studied the p-channel (p-ch.) poly silicon (Si) thin film transistor (TFT) using ultra low temperature processes below 200°C. By performing the low temperature thermal annealing after obtaining TFT, the device performances, such as the mobility of 64 cm cm2/Vs, and the sub-threshold slope (S.S) of 0.74 Vldec., improved drastically. The p-ch. circuits or complementary MOS (CMOS) design on plastic is expected for future advanced flexible flat panel display (FPD).
|Number of pages||3|
|Publication status||Published - 2005 Dec 1|
|Event||IDW/AD'05 - 12th International Display Workshops in Conjunction with Asia Display 2005 - Takamatsu, Japan|
Duration: 2005 Dec 6 → 2005 Dec 9
|Other||IDW/AD'05 - 12th International Display Workshops in Conjunction with Asia Display 2005|
|Period||05/12/6 → 05/12/9|
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