The Formation of Ti-Polycide Gate Structure with High Thermal Stability Using Chemical-Mechanical Polishing (CMP) Planarization Technology

Hyoung Sub Kim, Dae Hong Ko, Dae Lok Bae, Kazuyuki Fujihara, Ho Kyu Kang

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

A planarized Ti-polycide gate structure with high thermal stability has been developed using a chemical-mechanical polishing (CMP) process for the application of high-speed DRAM devices. For a given gate length and without any thermal annealing, the planarized Ti-polycide structure developed via a novel gate line formation technology manifested a substantially lower gate line resistance than that produced by a conventional processing method. In addition, the agglomeration of the TiSi2 gate in a deep submicron regime was suppressed even after high-temperature cycling at 850°C for 300 min, owing to a negligible local stress at the corner of the active and field region.

Original languageEnglish
Pages (from-to)86-88
Number of pages3
JournalIEEE Electron Device Letters
Volume20
Issue number2
DOIs
Publication statusPublished - 1999 Feb 1

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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