The hyperdynamic architecture (massively parallel message-passing machine) - Architecture and performance

Hojung Cha, Peter Jones

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The performance of message passing architecture machines is often ameliorated by devising alternative message passing strategies. A number have been proposed for incorporation into the design of architectures for massively parallel machines. Among these approaches are (i) static machine topologies supporting packet switched message routing (store-and-forward) (ii) dynamic machine topologies supporting circuit switched routing and (iii) shared memory systems. This paper reports the results of analytical modelling of these strategies - verifying the results by experimentation on a large reconfigurable transputer machine (the ParSiFal T-Rack). A family of hybrid architectures called the Hyper-Dynamic Architecture is then proposed which incorporates both packet switched and circuit switched features. Extrapolation of the verified analytical models and various simulation results obtained under realistic environments then allow some prediction of the potential performance of such architectures.

Original languageEnglish
Title of host publicationICS 1991 - Proceedings of the 5th International Conference on Supercomputing
EditorsEdward S. Davidson, Friedel Hossfield
PublisherAssociation for Computing Machinery
Pages9-19
Number of pages11
ISBN (Print)0897914341, 9780897914345
DOIs
Publication statusPublished - 1991 Jun 1
Event5th International Conference on Supercomputing, ICS 1991 - Cologne, Germany
Duration: 1991 Jun 171991 Jun 21

Publication series

NameProceedings of the International Conference on Supercomputing

Conference

Conference5th International Conference on Supercomputing, ICS 1991
CountryGermany
CityCologne
Period91/6/1791/6/21

All Science Journal Classification (ASJC) codes

  • Computer Science(all)

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    Cha, H., & Jones, P. (1991). The hyperdynamic architecture (massively parallel message-passing machine) - Architecture and performance. In E. S. Davidson, & F. Hossfield (Eds.), ICS 1991 - Proceedings of the 5th International Conference on Supercomputing (pp. 9-19). (Proceedings of the International Conference on Supercomputing). Association for Computing Machinery. https://doi.org/10.1145/109025.109031