The impact of dislocation on bulk-Si FinFET technologies: Physical modeling of strain relaxation and enhancement by dislocation

Jeong Guk Min; Changwook Jeong; Uihui Kwon; Dae Sin Kim; Suhyun Kim; Ilryoung Kim; Joon Sung Yang

doi:10.1109/NMDC.2018.8605736

The impact of dislocation on bulk-Si FinFET technologies: Physical modeling of strain relaxation and enhancement by dislocation

Jeong Guk Min, Changwook Jeong, Uihui Kwon, Dae Sin Kim, Suhyun Kim, Ilryoung Kim, Joon Sung Yang

College of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

The optimal position of dislocation stress memorization technique (DSMT) to maximize n-FinFET performance as well as the stacking fault (SF) number, [Ge] concentration limit and p-FinFET DC tradeoff in eSiGe are newly investigated by using the scanning moiré fringe (SMF) and scanning transmission electron microscopy-geometrical phase analysis (STEM-GPA) validated in-house 3D TCAD model in various bulk finFET structures.

Original language	English
Title of host publication	2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538610169
DOIs	https://doi.org/10.1109/NMDC.2018.8605736
Publication status	Published - 2019 Jan 8
Event	13th IEEE Nanotechnology Materials and Devices Conference, NMDC 2018 - Portland, United States Duration: 2018 Oct 14 → 2018 Oct 17

Publication series

Name	2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018

Conference

Conference	13th IEEE Nanotechnology Materials and Devices Conference, NMDC 2018
Country/Territory	United States
City	Portland
Period	18/10/14 → 18/10/17

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials
Surfaces, Coatings and Films
Instrumentation

Access to Document

10.1109/NMDC.2018.8605736

Cite this

Min, J. G., Jeong, C., Kwon, U., Kim, D. S., Kim, S., Kim, I., & Yang, J. S. (2019). The impact of dislocation on bulk-Si FinFET technologies: Physical modeling of strain relaxation and enhancement by dislocation. In 2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018 [8605736] (2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NMDC.2018.8605736

Min, Jeong Guk ; Jeong, Changwook ; Kwon, Uihui et al. / The impact of dislocation on bulk-Si FinFET technologies : Physical modeling of strain relaxation and enhancement by dislocation. 2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018. Institute of Electrical and Electronics Engineers Inc., 2019. (2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018).

@inproceedings{69e9e4b5fdb342479faaceabd7c2c348,

title = "The impact of dislocation on bulk-Si FinFET technologies: Physical modeling of strain relaxation and enhancement by dislocation",

abstract = "The optimal position of dislocation stress memorization technique (DSMT) to maximize n-FinFET performance as well as the stacking fault (SF) number, [Ge] concentration limit and p-FinFET DC tradeoff in eSiGe are newly investigated by using the scanning moir{\'e} fringe (SMF) and scanning transmission electron microscopy-geometrical phase analysis (STEM-GPA) validated in-house 3D TCAD model in various bulk finFET structures.",

author = "Min, {Jeong Guk} and Changwook Jeong and Uihui Kwon and Kim, {Dae Sin} and Suhyun Kim and Ilryoung Kim and Yang, {Joon Sung}",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 13th IEEE Nanotechnology Materials and Devices Conference, NMDC 2018 ; Conference date: 14-10-2018 Through 17-10-2018",

year = "2019",

month = jan,

day = "8",

doi = "10.1109/NMDC.2018.8605736",

language = "English",

series = "2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018",

address = "United States",

}

Min, JG, Jeong, C, Kwon, U, Kim, DS, Kim, S, Kim, I & Yang, JS 2019, The impact of dislocation on bulk-Si FinFET technologies: Physical modeling of strain relaxation and enhancement by dislocation. in 2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018., 8605736, 2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018, Institute of Electrical and Electronics Engineers Inc., 13th IEEE Nanotechnology Materials and Devices Conference, NMDC 2018, Portland, United States, 18/10/14. https://doi.org/10.1109/NMDC.2018.8605736

The impact of dislocation on bulk-Si FinFET technologies : Physical modeling of strain relaxation and enhancement by dislocation. / Min, Jeong Guk; Jeong, Changwook; Kwon, Uihui et al.

2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018. Institute of Electrical and Electronics Engineers Inc., 2019. 8605736 (2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - The impact of dislocation on bulk-Si FinFET technologies

T2 - 13th IEEE Nanotechnology Materials and Devices Conference, NMDC 2018

AU - Min, Jeong Guk

AU - Jeong, Changwook

AU - Kwon, Uihui

AU - Kim, Dae Sin

AU - Kim, Suhyun

AU - Kim, Ilryoung

AU - Yang, Joon Sung

PY - 2019/1/8

Y1 - 2019/1/8

N2 - The optimal position of dislocation stress memorization technique (DSMT) to maximize n-FinFET performance as well as the stacking fault (SF) number, [Ge] concentration limit and p-FinFET DC tradeoff in eSiGe are newly investigated by using the scanning moiré fringe (SMF) and scanning transmission electron microscopy-geometrical phase analysis (STEM-GPA) validated in-house 3D TCAD model in various bulk finFET structures.

AB - The optimal position of dislocation stress memorization technique (DSMT) to maximize n-FinFET performance as well as the stacking fault (SF) number, [Ge] concentration limit and p-FinFET DC tradeoff in eSiGe are newly investigated by using the scanning moiré fringe (SMF) and scanning transmission electron microscopy-geometrical phase analysis (STEM-GPA) validated in-house 3D TCAD model in various bulk finFET structures.

UR - http://www.scopus.com/inward/record.url?scp=85061784248&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85061784248&partnerID=8YFLogxK

U2 - 10.1109/NMDC.2018.8605736

DO - 10.1109/NMDC.2018.8605736

M3 - Conference contribution

AN - SCOPUS:85061784248

T3 - 2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018

BT - 2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 14 October 2018 through 17 October 2018

ER -

Min JG, Jeong C, Kwon U, Kim DS, Kim S, Kim I et al. The impact of dislocation on bulk-Si FinFET technologies: Physical modeling of strain relaxation and enhancement by dislocation. In 2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018. Institute of Electrical and Electronics Engineers Inc. 2019. 8605736. (2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018). doi: 10.1109/NMDC.2018.8605736

The impact of dislocation on bulk-Si FinFET technologies: Physical modeling of strain relaxation and enhancement by dislocation

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