The impact of dislocation on bulk-Si FinFET technologies: Physical modeling of strain relaxation and enhancement by dislocation

Jeong Guk Min, Changwook Jeong, Uihui Kwon, Dae Sin Kim, Suhyun Kim, Ilryoung Kim, Joon Sung Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The optimal position of dislocation stress memorization technique (DSMT) to maximize n-FinFET performance as well as the stacking fault (SF) number, [Ge] concentration limit and p-FinFET DC tradeoff in eSiGe are newly investigated by using the scanning moiré fringe (SMF) and scanning transmission electron microscopy-geometrical phase analysis (STEM-GPA) validated in-house 3D TCAD model in various bulk finFET structures.

Original languageEnglish
Title of host publication2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538610169
DOIs
Publication statusPublished - 2019 Jan 8
Event13th IEEE Nanotechnology Materials and Devices Conference, NMDC 2018 - Portland, United States
Duration: 2018 Oct 142018 Oct 17

Publication series

Name2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018

Conference

Conference13th IEEE Nanotechnology Materials and Devices Conference, NMDC 2018
Country/TerritoryUnited States
CityPortland
Period18/10/1418/10/17

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Surfaces, Coatings and Films
  • Instrumentation

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