The optimal position of dislocation stress memorization technique (DSMT) to maximize n-FinFET performance as well as the stacking fault (SF) number, [Ge] concentration limit and p-FinFET DC tradeoff in eSiGe are newly investigated by using the scanning moiré fringe (SMF) and scanning transmission electron microscopy-geometrical phase analysis (STEM-GPA) validated in-house 3D TCAD model in various bulk finFET structures.
|Title of host publication||2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Publication status||Published - 2019 Jan 8|
|Event||13th IEEE Nanotechnology Materials and Devices Conference, NMDC 2018 - Portland, United States|
Duration: 2018 Oct 14 → 2018 Oct 17
|Name||2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018|
|Conference||13th IEEE Nanotechnology Materials and Devices Conference, NMDC 2018|
|Period||18/10/14 → 18/10/17|
Bibliographical notePublisher Copyright:
© 2018 IEEE.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
- Surfaces, Coatings and Films