The impact of gate-to-drain (GtD) spacing on hot carrier reliability in sub-100 nm Ni-Pt self-aligned silicided FinFETs has been analyzed experimentally. FinFETs with long GtD spaces exhibit severe drain current degradation (ΔIDS/IDS), but variations in threshold voltage (ΔVTH/VTH) and subthreshold swing (ΔSS/SS) are nearly the same as with short GtD spaces. When gate length (LG) is downscaled from 1 μm to 40 nm, the degradation between long and short GtD spaces increases from 0.4% to 6.5%. The amount of injected hot electrons into salicide-induced defects in the silicon region accounts for the dominant portion of the difference in the current degradation between short and long GtD spaces. The dependence of hot carrier immunity on GtD spacing has been analyzed by both qualitative and quantitative methods.
Bibliographical noteFunding Information:
This work was supported by the Future Semiconductor Device Technology Development Program (10044735, 10048536) funded by MOTIE and KSRC; IT R&D program of MOTIE/KEIT (10048931); and the MSIP, Korea, under the “IT Consilience Creative Program” (IITP-2015-R0346-15-1008) supervised by NIPA.
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Materials Chemistry