Thermal aware test scheduling for NTV circuit

Jaeil Lim, Hyunggoy Oh, Heetae Kim, Sungho Kang

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Although the near threshold voltage (NTV) design has achieved energy efficiency, certain challenges remain regarding its application. In this paper, we describe the analysis of thermally induced reliability concern in test process. In an NTV environment, the thermal dependency of a circuit delay is changed, and a difference in thermal constraints from that in a nominal voltage design exists. In addition, we propose a new test scheduling method for NTV circuits that alleviates the thermal constraints in system-on-chip test processes. Our simulation results show that the test time could be reduced while minimizing the reliability loss.

Original languageEnglish
Article number7984890
Pages (from-to)906-910
Number of pages5
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume37
Issue number4
DOIs
Publication statusPublished - 2018 Apr 1

Fingerprint

Threshold voltage
Scheduling
Networks (circuits)
Delay circuits
Energy efficiency
Electric potential
Hot Temperature

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

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Thermal aware test scheduling for NTV circuit. / Lim, Jaeil; Oh, Hyunggoy; Kim, Heetae; Kang, Sungho.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 37, No. 4, 7984890, 01.04.2018, p. 906-910.

Research output: Contribution to journalArticle

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