Thermal aware test scheduling for NTV circuit

Jaeil Lim, Hyunggoy Oh, Heetae Kim, Sungho Kang

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


Although the near threshold voltage (NTV) design has achieved energy efficiency, certain challenges remain regarding its application. In this paper, we describe the analysis of thermally induced reliability concern in test process. In an NTV environment, the thermal dependency of a circuit delay is changed, and a difference in thermal constraints from that in a nominal voltage design exists. In addition, we propose a new test scheduling method for NTV circuits that alleviates the thermal constraints in system-on-chip test processes. Our simulation results show that the test time could be reduced while minimizing the reliability loss.

Original languageEnglish
Article number7984890
Pages (from-to)906-910
Number of pages5
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number4
Publication statusPublished - 2018 Apr

Bibliographical note

Funding Information:
Manuscript received September 8, 2016; revised January 23, 2017 and June 12, 2017; accepted July 7, 2017. Date of publication July 19, 2017; date of current version March 29, 2018. This work was supported by a National Research Foundation of Korea (NRF) grant funded by the Korean government (MEST) (No. 2015R1A2A1A13001751). This paper was recommended by Associate Editor A. E. Gattiker. (Corresponding author: Sungho Kang.) The authors are with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul 03722, South Korea (e-mail:;;;

Publisher Copyright:
© 2017 IEEE.

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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