Thermal modeling of 7 nm node bulk fin-shaped field-effect transistors for device structure-aware design

Chuntaek Park, Ilgu Yun

Research output: Contribution to journalArticle

Abstract

As semiconductor node technology becomes finer, the corresponding device dimensions should be reduced. To improve the side effects caused by the scaling-down strategy, fin-shaped field-effect transistors (FinFETs) have been introduced and are being actively researched. However, these thin silicon fins, especially confined within silicon dioxide (SiO2), have a relatively low thermal conductivity when compared with conventional planar bulk FETs. Thus, another issue, called the self-heating effect (SHE), has appeared with the emergence of FinFETs. In this paper, the self-heating effect on 7 nm node bulk FinFETs was investigated through calibrated technology computer-aided design (TCAD) simulation. A thermodynamic transport model is used to consider the self-heating effect on the device. The thermal resistance (R TH) was extracted from the TCAD result and modeled empirically to predict the R TH of sub-7 nm node technology. The empirical R TH model was also implanted in a Berkeley short-channel IGFET model-common multi-gate (BSIM-CMG) to conduct an accurate Simulation Program with Integrated Circuit Emphasis (SPICE) model and simulation.

Original languageEnglish
Article number115014
JournalSemiconductor Science and Technology
Volume33
Issue number11
DOIs
Publication statusPublished - 2018 Oct 15

Fingerprint

fins
Field effect transistors
field effect transistors
Heating
Computer aided design
computer aided design
heating
Silicon
Heat resistance
Silicon Dioxide
simulation
Integrated circuits
Thermal conductivity
thermal resistance
Silica
Thermodynamics
integrated circuits
Semiconductor materials
thermal conductivity
Hot Temperature

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

Cite this

@article{4d1ee771f55e41079d4390508a9dab34,
title = "Thermal modeling of 7 nm node bulk fin-shaped field-effect transistors for device structure-aware design",
abstract = "As semiconductor node technology becomes finer, the corresponding device dimensions should be reduced. To improve the side effects caused by the scaling-down strategy, fin-shaped field-effect transistors (FinFETs) have been introduced and are being actively researched. However, these thin silicon fins, especially confined within silicon dioxide (SiO2), have a relatively low thermal conductivity when compared with conventional planar bulk FETs. Thus, another issue, called the self-heating effect (SHE), has appeared with the emergence of FinFETs. In this paper, the self-heating effect on 7 nm node bulk FinFETs was investigated through calibrated technology computer-aided design (TCAD) simulation. A thermodynamic transport model is used to consider the self-heating effect on the device. The thermal resistance (R TH) was extracted from the TCAD result and modeled empirically to predict the R TH of sub-7 nm node technology. The empirical R TH model was also implanted in a Berkeley short-channel IGFET model-common multi-gate (BSIM-CMG) to conduct an accurate Simulation Program with Integrated Circuit Emphasis (SPICE) model and simulation.",
author = "Chuntaek Park and Ilgu Yun",
year = "2018",
month = "10",
day = "15",
doi = "10.1088/1361-6641/aae2ea",
language = "English",
volume = "33",
journal = "Semiconductor Science and Technology",
issn = "0268-1242",
publisher = "IOP Publishing Ltd.",
number = "11",

}

Thermal modeling of 7 nm node bulk fin-shaped field-effect transistors for device structure-aware design. / Park, Chuntaek; Yun, Ilgu.

In: Semiconductor Science and Technology, Vol. 33, No. 11, 115014, 15.10.2018.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Thermal modeling of 7 nm node bulk fin-shaped field-effect transistors for device structure-aware design

AU - Park, Chuntaek

AU - Yun, Ilgu

PY - 2018/10/15

Y1 - 2018/10/15

N2 - As semiconductor node technology becomes finer, the corresponding device dimensions should be reduced. To improve the side effects caused by the scaling-down strategy, fin-shaped field-effect transistors (FinFETs) have been introduced and are being actively researched. However, these thin silicon fins, especially confined within silicon dioxide (SiO2), have a relatively low thermal conductivity when compared with conventional planar bulk FETs. Thus, another issue, called the self-heating effect (SHE), has appeared with the emergence of FinFETs. In this paper, the self-heating effect on 7 nm node bulk FinFETs was investigated through calibrated technology computer-aided design (TCAD) simulation. A thermodynamic transport model is used to consider the self-heating effect on the device. The thermal resistance (R TH) was extracted from the TCAD result and modeled empirically to predict the R TH of sub-7 nm node technology. The empirical R TH model was also implanted in a Berkeley short-channel IGFET model-common multi-gate (BSIM-CMG) to conduct an accurate Simulation Program with Integrated Circuit Emphasis (SPICE) model and simulation.

AB - As semiconductor node technology becomes finer, the corresponding device dimensions should be reduced. To improve the side effects caused by the scaling-down strategy, fin-shaped field-effect transistors (FinFETs) have been introduced and are being actively researched. However, these thin silicon fins, especially confined within silicon dioxide (SiO2), have a relatively low thermal conductivity when compared with conventional planar bulk FETs. Thus, another issue, called the self-heating effect (SHE), has appeared with the emergence of FinFETs. In this paper, the self-heating effect on 7 nm node bulk FinFETs was investigated through calibrated technology computer-aided design (TCAD) simulation. A thermodynamic transport model is used to consider the self-heating effect on the device. The thermal resistance (R TH) was extracted from the TCAD result and modeled empirically to predict the R TH of sub-7 nm node technology. The empirical R TH model was also implanted in a Berkeley short-channel IGFET model-common multi-gate (BSIM-CMG) to conduct an accurate Simulation Program with Integrated Circuit Emphasis (SPICE) model and simulation.

UR - http://www.scopus.com/inward/record.url?scp=85055348272&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85055348272&partnerID=8YFLogxK

U2 - 10.1088/1361-6641/aae2ea

DO - 10.1088/1361-6641/aae2ea

M3 - Article

VL - 33

JO - Semiconductor Science and Technology

JF - Semiconductor Science and Technology

SN - 0268-1242

IS - 11

M1 - 115014

ER -