Thermal-stress stability of yttrium oxide as a buffer layer of metal-ferroelectric-insulator-semiconductor field effect transistor

Chang Ki Lee, Woo Sik Kim, Hyung-Ho Park, Hyeongtag Jeon, Yeon Ho Pae

Research output: Contribution to journalArticle

11 Citations (Scopus)

Abstract

The effect of thermal stress on the electrical properties of ferroelectric/semiconductor structure was investigated when introducing Y 2O3 film as a barrier layer in the structure. Two different thermal stress states could be obtained by fast (400 °C/min) or slow (30 °C/min) cooling of sputter-deposited Y2O3 films on silicon wafer from 800 °C. The formation of interfacial layer containing Y-Si-O and SiO2 layers while annealing could be characterized by using a spectroscopic ellipsometry. The introduction of strain-induced defects from thermal stress of the fast cooled sample showed a soft breakdown at low applying voltage. In the capacitance-voltage relation, a flat band voltage shift, hysteresis, and stretch-out phenomena were also observed. Nd2Ti2O7 was spin deposited using sol-gel procedure on the Y2O3/Si to form a metal-ferroelectric-insulator field effect transistor structured sample. These Nd2Ti2O7/Y2O3/Si samples were also furnace-annealed at 800 °C and cooled down to room temperature fast or slowly. One order lower value of leakage current, IE-8 A/cm2 was observed with these samples when comparing with the Y2O 3/Si samples. A soft breakdown of the fast cooled sample seemed to have the same origin as the fast cooled Y2O3/Si sample, i.e., the strain-induced defects in the interfacial layer containing Y-Si-O and SiO2 phases. Hysteretic gaps of the Nd2Ti2CV Y2O3/Si samples showed a possibility to be used as a memory window for ferroelectric gate.

Original languageEnglish
Pages (from-to)335-339
Number of pages5
JournalThin Solid Films
Volume473
Issue number2
DOIs
Publication statusPublished - 2005 Jan 1

Fingerprint

yttrium oxides
Yttrium oxide
Buffer layers
thermal stresses
Field effect transistors
Thermal stress
Ferroelectric materials
field effect transistors
buffers
Metals
insulators
Semiconductor materials
Electric potential
metals
Defects
Spectroscopic ellipsometry
Silicon wafers
Leakage currents
Sol-gels
Hysteresis

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Surfaces and Interfaces
  • Surfaces, Coatings and Films
  • Metals and Alloys
  • Materials Chemistry

Cite this

Lee, Chang Ki ; Kim, Woo Sik ; Park, Hyung-Ho ; Jeon, Hyeongtag ; Pae, Yeon Ho. / Thermal-stress stability of yttrium oxide as a buffer layer of metal-ferroelectric-insulator-semiconductor field effect transistor. In: Thin Solid Films. 2005 ; Vol. 473, No. 2. pp. 335-339.
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Thermal-stress stability of yttrium oxide as a buffer layer of metal-ferroelectric-insulator-semiconductor field effect transistor. / Lee, Chang Ki; Kim, Woo Sik; Park, Hyung-Ho; Jeon, Hyeongtag; Pae, Yeon Ho.

In: Thin Solid Films, Vol. 473, No. 2, 01.01.2005, p. 335-339.

Research output: Contribution to journalArticle

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T1 - Thermal-stress stability of yttrium oxide as a buffer layer of metal-ferroelectric-insulator-semiconductor field effect transistor

AU - Lee, Chang Ki

AU - Kim, Woo Sik

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N2 - The effect of thermal stress on the electrical properties of ferroelectric/semiconductor structure was investigated when introducing Y 2O3 film as a barrier layer in the structure. Two different thermal stress states could be obtained by fast (400 °C/min) or slow (30 °C/min) cooling of sputter-deposited Y2O3 films on silicon wafer from 800 °C. The formation of interfacial layer containing Y-Si-O and SiO2 layers while annealing could be characterized by using a spectroscopic ellipsometry. The introduction of strain-induced defects from thermal stress of the fast cooled sample showed a soft breakdown at low applying voltage. In the capacitance-voltage relation, a flat band voltage shift, hysteresis, and stretch-out phenomena were also observed. Nd2Ti2O7 was spin deposited using sol-gel procedure on the Y2O3/Si to form a metal-ferroelectric-insulator field effect transistor structured sample. These Nd2Ti2O7/Y2O3/Si samples were also furnace-annealed at 800 °C and cooled down to room temperature fast or slowly. One order lower value of leakage current, IE-8 A/cm2 was observed with these samples when comparing with the Y2O 3/Si samples. A soft breakdown of the fast cooled sample seemed to have the same origin as the fast cooled Y2O3/Si sample, i.e., the strain-induced defects in the interfacial layer containing Y-Si-O and SiO2 phases. Hysteretic gaps of the Nd2Ti2CV Y2O3/Si samples showed a possibility to be used as a memory window for ferroelectric gate.

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