Thickness Dependence of Gate Dielectric Layer on Structural and Electrical Characteristics in the Pentacene Thin-Film Transistors

Chang Su Kim, Sung Jin Jo, Sung Won Lee, Woo Jin Kim, Hong Koo Baik, Se Jong Lee

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

We report on the fabrication of low-voltage pentacene thin-film transistors (TFTs) with CeO2 - SiO2 composite dielectric layers in the thickness range of 20 to 300 nm. The maximum field effect mobility of 0.97 cm2 V s and on/off current ratio of 104 were achieved under a low operating voltage of -2 V from our pentacene TFTs with 50 nm thin CeO2 - SiO2 composite dielectric layer. The capacitance and surface smoothness of the dielectric layer were improved with lowering the dielectric thickness. Pentacene TFTs with thin dielectric layers were thus found to be generally superior to the others with thick dielectric layers in device performance although the dielectric also showed its own thickness limit in enduring the 2 V gate bias. We conclude that there is an optimum dielectric thickness for the most desirable device performance and that our TFTs with the 50 nm thin gate dielectric have demonstrated the performance.

Original languageEnglish
JournalJournal of the Electrochemical Society
Volume154
Issue number2
DOIs
Publication statusPublished - 2007 Jan 19

Fingerprint

Gate dielectrics
Thin film transistors
transistors
thin films
pentacene
Composite materials
Electric potential
composite materials
low voltage
Capacitance
capacitance
Fabrication
fabrication
electric potential

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Renewable Energy, Sustainability and the Environment
  • Surfaces, Coatings and Films
  • Electrochemistry
  • Materials Chemistry

Cite this

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abstract = "We report on the fabrication of low-voltage pentacene thin-film transistors (TFTs) with CeO2 - SiO2 composite dielectric layers in the thickness range of 20 to 300 nm. The maximum field effect mobility of 0.97 cm2 V s and on/off current ratio of 104 were achieved under a low operating voltage of -2 V from our pentacene TFTs with 50 nm thin CeO2 - SiO2 composite dielectric layer. The capacitance and surface smoothness of the dielectric layer were improved with lowering the dielectric thickness. Pentacene TFTs with thin dielectric layers were thus found to be generally superior to the others with thick dielectric layers in device performance although the dielectric also showed its own thickness limit in enduring the 2 V gate bias. We conclude that there is an optimum dielectric thickness for the most desirable device performance and that our TFTs with the 50 nm thin gate dielectric have demonstrated the performance.",
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Thickness Dependence of Gate Dielectric Layer on Structural and Electrical Characteristics in the Pentacene Thin-Film Transistors. / Kim, Chang Su; Jo, Sung Jin; Lee, Sung Won; Kim, Woo Jin; Baik, Hong Koo; Lee, Se Jong.

In: Journal of the Electrochemical Society, Vol. 154, No. 2, 19.01.2007.

Research output: Contribution to journalArticle

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T1 - Thickness Dependence of Gate Dielectric Layer on Structural and Electrical Characteristics in the Pentacene Thin-Film Transistors

AU - Kim, Chang Su

AU - Jo, Sung Jin

AU - Lee, Sung Won

AU - Kim, Woo Jin

AU - Baik, Hong Koo

AU - Lee, Se Jong

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AB - We report on the fabrication of low-voltage pentacene thin-film transistors (TFTs) with CeO2 - SiO2 composite dielectric layers in the thickness range of 20 to 300 nm. The maximum field effect mobility of 0.97 cm2 V s and on/off current ratio of 104 were achieved under a low operating voltage of -2 V from our pentacene TFTs with 50 nm thin CeO2 - SiO2 composite dielectric layer. The capacitance and surface smoothness of the dielectric layer were improved with lowering the dielectric thickness. Pentacene TFTs with thin dielectric layers were thus found to be generally superior to the others with thick dielectric layers in device performance although the dielectric also showed its own thickness limit in enduring the 2 V gate bias. We conclude that there is an optimum dielectric thickness for the most desirable device performance and that our TFTs with the 50 nm thin gate dielectric have demonstrated the performance.

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