Thread-Aware Area-Efficient High-Level Synthesis Compiler for Embedded Devices

Changsu Kim, Shinnung Jeong, Sungjun Cho, Yongwoo Lee, William Song, Youngsok Kim, Hanjun Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In the embedded device market, custom hardware platforms such as an application specific integrated circuit (ASIC) and a field programmable gate array (FPGA) are attractive thanks to their high performance and power efficiency. However, its huge design costs make it challenging for manufacturers to timely launch new devices. High-level synthesis (HLS) helps significantly reduce the design costs by automating the translation of service algorithms into hardware logics; however, current HLS compilers do not fit well to embedded devices as they fail to produce area-efficient solutions while supporting concurrent events from diverse peripherals such as sensors, actuators and network modules. This paper proposes a new thread-aware HLS compiler named Duro that produces area-efficient embedded devices. Duro shares commonly-invoked functions and operators across different callers and threads with a new thread-aware area cost model, and thus effectively reduces the logic size. Moreover, Duro supports a variety of device peripherals by automatically integrating peripheral controllers and interfaces as peripheral drivers. The experiment results of six embedded devices with ten peripherals demonstrate that Duro reduces the area and energy dissipation of embedded devices by 28.5% and 25.3% compared with the designs generated by the state-of-the-art HLS compiler. This work also implements FPGA prototypes of the six devices using Duro, and the measurement results show 65.3% energy saving over Raspberry Pi Zero with slightly better computation performance.

Original languageEnglish
Title of host publicationCGO 2021 - Proceedings of the 2021 IEEE/ACM International Symposium on Code Generation and Optimization
EditorsJae W. Lee, Mary Lou Soffa, Ayal Zaks
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages327-339
Number of pages13
ISBN (Electronic)9781728186139
DOIs
Publication statusPublished - 2021 Feb 27
Event19th IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2021 - Virtual, Korea, Korea, Republic of
Duration: 2021 Feb 272021 Mar 3

Publication series

NameCGO 2021 - Proceedings of the 2021 IEEE/ACM International Symposium on Code Generation and Optimization

Conference

Conference19th IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2021
CountryKorea, Republic of
CityVirtual, Korea
Period21/2/2721/3/3

Bibliographical note

Funding Information:
We thank the anonymous reviewers for their insightful comments and suggestions. We also thank the CoreLab members for their support and feedback during this work. This work is supported by IITP-2018-0-01392 and IITP-2020-0-01847 through the Institute of Information and Communication Technology Planning and Evaluation (IITP) funded by the Ministry of Science and ICT. This work is also supported by Samsung Electronics. (Corresponding author: Hanjun Kim)

Publisher Copyright:
© 2021 IEEE.

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Software
  • Control and Optimization

Fingerprint Dive into the research topics of 'Thread-Aware Area-Efficient High-Level Synthesis Compiler for Embedded Devices'. Together they form a unique fingerprint.

Cite this