Threshold voltage shift prediction for gate bias stress on amorphous InGaZnO thin film transistors

The demand for amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) has increased due to the high mobility and suitability for low temperature fabrication. A prediction of the threshold voltage shift (ΔV _th) under bias stress is required for the commercial use of a-IGZO TFTs. We have investigated effects of the channel length and alternating pulse bias (positive and negative gate bias stress in sequence) with different positive gate bias values (V _GS+) on ΔV _th. We found that ΔV _th increases as the channel length decreases or V _GS+ increases, due to the increase in the charge trapping rate. Finally, the degradation behaviors of a-IGZO TFTs are predicted.