The demand for amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) has increased due to the high mobility and suitability for low temperature fabrication. A prediction of the threshold voltage shift (ΔV th) under bias stress is required for the commercial use of a-IGZO TFTs. We have investigated effects of the channel length and alternating pulse bias (positive and negative gate bias stress in sequence) with different positive gate bias values (V GS+) on ΔV th. We found that ΔV th increases as the channel length decreases or V GS+ increases, due to the increase in the charge trapping rate. Finally, the degradation behaviors of a-IGZO TFTs are predicted.
Bibliographical noteFunding Information:
This work was supported by Yonsei University, Institute of TMS Information Technology, a Brain Korea 21 program, Korea.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Atomic and Molecular Physics, and Optics
- Safety, Risk, Reliability and Quality
- Condensed Matter Physics
- Surfaces, Coatings and Films
- Electrical and Electronic Engineering